// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date        : Tue Dec 22 19:10:30 2015
// Host        : jon-GA-MA770T-ES3 running 64-bit Linux Mint 17.2 Rafaela
// Command     : write_verilog -force ./cpu_impl_netlist.v -mode timesim -sdf_anno true
// Design      : BSP
// Purpose     : This verilog netlist is a timing simulation representation of the design and should not be modified or
//               synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device      : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING

module BRAM
   (DOBDO,
    ETH_CLK_OBUF,
    ADDRBWRADDR,
    pwropt);
  output [3:0]DOBDO;
  input ETH_CLK_OBUF;
  input [12:0]ADDRBWRADDR;
  input pwropt;

  wire [12:0]ADDRBWRADDR;
  wire [3:0]DOBDO;
  wire ETH_CLK_OBUF;
  wire pwropt;
  wire NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED;
  wire NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED;
  wire NLW_MEMORY_reg_0_DBITERR_UNCONNECTED;
  wire NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED;
  wire NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED;
  wire NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED;
  wire NLW_MEMORY_reg_0_REGCEB_UNCONNECTED;
  wire NLW_MEMORY_reg_0_SBITERR_UNCONNECTED;
  wire [31:0]NLW_MEMORY_reg_0_DOADO_UNCONNECTED;
  wire [31:4]NLW_MEMORY_reg_0_DOBDO_UNCONNECTED;
  wire [3:0]NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED;

  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENBWREN=NEW" *) 
  (* RTL_RAM_BITS = "60000" *) 
  (* RTL_RAM_NAME = "MEMORY" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "0" *) 
  (* bram_slice_end = "3" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .IS_ENBWREN_INVERTED(1'b1),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(4),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(4)) 
    MEMORY_reg_0
       (.ADDRARDADDR({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b1),
        .CASCADEOUTA(NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(ETH_CLK_OBUF),
        .DBITERR(NLW_MEMORY_reg_0_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(NLW_MEMORY_reg_0_DOADO_UNCONNECTED[31:0]),
        .DOBDO({NLW_MEMORY_reg_0_DOBDO_UNCONNECTED[31:4],DOBDO}),
        .DOPADOP(NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(1'b1),
        .ENBWREN(pwropt),
        .INJECTDBITERR(NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_MEMORY_reg_0_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_MEMORY_reg_0_SBITERR_UNCONNECTED),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ECO_CHECKSUM = "395b7b4d" *) (* POWER_OPT_BRAM_CDC = "0" *) (* POWER_OPT_BRAM_SR_ADDR = "0" *) 
(* POWER_OPT_LOOPED_NET_PERCENTAGE = "0" *) 
(* NotValidForBitStream *)
module BSP
   (CLK_IN,
    RST,
    ETH_CLK,
    PHY_RESET_N,
    RXDV,
    RXER,
    RXD,
    TXD,
    TXEN,
    JC,
    SDA,
    SCL,
    KD,
    KC,
    AUDIO,
    AUDIO_EN,
    VGA_R,
    VGA_G,
    VGA_B,
    HSYNCH,
    VSYNCH,
    GPIO_LEDS,
    GPIO_SWITCHES,
    GPIO_BUTTONS,
    LED_R_PWM,
    LED_G_PWM,
    LED_B_PWM,
    SEVEN_SEGMENT_CATHODE,
    SEVEN_SEGMENT_ANNODE,
    RS232_RX,
    RS232_TX);
  input CLK_IN;
  input RST;
  output ETH_CLK;
  output PHY_RESET_N;
  input RXDV;
  input RXER;
  input [1:0]RXD;
  output [1:0]TXD;
  output TXEN;
  inout [7:0]JC;
  inout SDA;
  inout SCL;
  input KD;
  input KC;
  output AUDIO;
  output AUDIO_EN;
  output [3:0]VGA_R;
  output [3:0]VGA_G;
  output [3:0]VGA_B;
  output HSYNCH;
  output VSYNCH;
  output [15:0]GPIO_LEDS;
  input [15:0]GPIO_SWITCHES;
  input [4:0]GPIO_BUTTONS;
  output LED_R_PWM;
  output LED_G_PWM;
  output LED_B_PWM;
  output [6:0]SEVEN_SEGMENT_CATHODE;
  output [7:0]SEVEN_SEGMENT_ANNODE;
  input RS232_RX;
  output RS232_TX;

  wire AUDIO;
  wire AUDIO_EN;
  wire CLKFB;
  wire CLKIN;
  (* IBUF_LOW_PWR *) wire CLK_IN;
  wire ETH_CLK;
  wire ETH_CLK_OBUF;
  wire \GPIO_BUTTONS[0] ;
  wire \GPIO_BUTTONS[0]_IBUF ;
  wire \GPIO_BUTTONS[1] ;
  wire \GPIO_BUTTONS[1]_IBUF ;
  wire \GPIO_BUTTONS[2] ;
  wire \GPIO_BUTTONS[2]_IBUF ;
  wire \GPIO_BUTTONS[3] ;
  wire \GPIO_BUTTONS[3]_IBUF ;
  wire \GPIO_BUTTONS[4] ;
  wire \GPIO_BUTTONS[4]_IBUF ;
  wire [15:0]GPIO_LEDS;
  wire \GPIO_SWITCHES[0] ;
  wire \GPIO_SWITCHES[0]_IBUF ;
  wire \GPIO_SWITCHES[10] ;
  wire \GPIO_SWITCHES[10]_IBUF ;
  wire \GPIO_SWITCHES[11] ;
  wire \GPIO_SWITCHES[11]_IBUF ;
  wire \GPIO_SWITCHES[12] ;
  wire \GPIO_SWITCHES[12]_IBUF ;
  wire \GPIO_SWITCHES[13] ;
  wire \GPIO_SWITCHES[13]_IBUF ;
  wire \GPIO_SWITCHES[14] ;
  wire \GPIO_SWITCHES[14]_IBUF ;
  wire \GPIO_SWITCHES[15] ;
  wire \GPIO_SWITCHES[15]_IBUF ;
  wire \GPIO_SWITCHES[1] ;
  wire \GPIO_SWITCHES[1]_IBUF ;
  wire \GPIO_SWITCHES[2] ;
  wire \GPIO_SWITCHES[2]_IBUF ;
  wire \GPIO_SWITCHES[3] ;
  wire \GPIO_SWITCHES[3]_IBUF ;
  wire \GPIO_SWITCHES[4] ;
  wire \GPIO_SWITCHES[4]_IBUF ;
  wire \GPIO_SWITCHES[5] ;
  wire \GPIO_SWITCHES[5]_IBUF ;
  wire \GPIO_SWITCHES[6] ;
  wire \GPIO_SWITCHES[6]_IBUF ;
  wire \GPIO_SWITCHES[7] ;
  wire \GPIO_SWITCHES[7]_IBUF ;
  wire \GPIO_SWITCHES[8] ;
  wire \GPIO_SWITCHES[8]_IBUF ;
  wire \GPIO_SWITCHES[9] ;
  wire \GPIO_SWITCHES[9]_IBUF ;
  wire HSYNCH;
  wire HSYNCH_OBUF;
  wire IN1_ACK;
  wire IN1_STB;
  wire INTERNAL_RST_reg_n_0;
  wire [7:0]JC;
  wire [1:1]JC_IBUF;
  wire KC;
  wire KC_IBUF;
  wire KD;
  wire KD_IBUF;
  wire LED_B_PWM;
  wire LED_B_PWM_OBUF;
  wire LED_G_PWM;
  wire LED_G_PWM_OBUF;
  wire LED_R_PWM;
  wire LED_R_PWM_OBUF;
  wire NOT_LOCKED;
  wire NOT_LOCKED_i_1_n_0;
  wire [7:0]OUT1;
  wire OUT1_ACK;
  wire OUT1_STB;
  wire PHY_RESET_N;
  wire PHY_RESET_N_OBUF;
  wire RS232_RX;
  wire RS232_RX_IBUF;
  wire RS232_TX;
  wire RS232_TX_OBUF;
  wire RST;
  wire RST_IBUF;
  wire RXDV;
  wire RXDV_IBUF;
  wire \RXD[0] ;
  wire \RXD[0]_IBUF ;
  wire \RXD[1] ;
  wire \RXD[1]_IBUF ;
  wire RXER;
  wire RXER_IBUF;
  (* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "SLOW" *) wire SCL;
  wire SCL_IBUF;
  wire SCL_TRI;
  wire SDA;
  wire SDA_IBUF;
  wire SDA_TRI;
  wire [7:0]SEVEN_SEGMENT_ANNODE;
  wire [6:0]SEVEN_SEGMENT_CATHODE;
  wire [1:0]TXD;
  wire [1:0]TXD_OBUF;
  wire TXEN;
  wire TXEN_OBUF;
  wire USER_DESIGN_INST_1_n_2;
  wire USER_DESIGN_INST_1_n_3;
  wire USER_DESIGN_INST_1_n_4;
  wire USER_DESIGN_INST_1_n_5;
  wire USER_DESIGN_INST_1_n_6;
  wire USER_DESIGN_INST_1_n_7;
  wire USER_DESIGN_INST_1_n_8;
  wire USER_DESIGN_INST_1_n_9;
  wire [3:0]VGA_B;
  wire [0:0]VGA_B_OBUF;
  wire [3:0]VGA_G;
  wire [3:0]VGA_R;
  wire VSYNCH;
  wire VSYNCH_OBUF;
  wire clk0;
  wire clkdv;
  wire locked_internal;
  wire NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED;
  wire NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED;
  wire NLW_dcm_sp_inst_DRDY_UNCONNECTED;
  wire NLW_dcm_sp_inst_PSDONE_UNCONNECTED;
  wire [15:0]NLW_dcm_sp_inst_DO_UNCONNECTED;
  wire NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED;
  wire NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED;
  wire [1:0]NLW_ethernet_inst_1_D_UNCONNECTED;
PULLUP pullup_KC
       (.O(KC));
PULLUP pullup_KD
       (.O(KD));

initial begin
 $sdf_annotate("cpu_impl_netlist.sdf",,,,"tool_control");
end
  assign \GPIO_BUTTONS[0]  = GPIO_BUTTONS[0];
  assign \GPIO_BUTTONS[1]  = GPIO_BUTTONS[1];
  assign \GPIO_BUTTONS[2]  = GPIO_BUTTONS[2];
  assign \GPIO_BUTTONS[3]  = GPIO_BUTTONS[3];
  assign \GPIO_BUTTONS[4]  = GPIO_BUTTONS[4];
  assign \GPIO_SWITCHES[0]  = GPIO_SWITCHES[0];
  assign \GPIO_SWITCHES[10]  = GPIO_SWITCHES[10];
  assign \GPIO_SWITCHES[11]  = GPIO_SWITCHES[11];
  assign \GPIO_SWITCHES[12]  = GPIO_SWITCHES[12];
  assign \GPIO_SWITCHES[13]  = GPIO_SWITCHES[13];
  assign \GPIO_SWITCHES[14]  = GPIO_SWITCHES[14];
  assign \GPIO_SWITCHES[15]  = GPIO_SWITCHES[15];
  assign \GPIO_SWITCHES[1]  = GPIO_SWITCHES[1];
  assign \GPIO_SWITCHES[2]  = GPIO_SWITCHES[2];
  assign \GPIO_SWITCHES[3]  = GPIO_SWITCHES[3];
  assign \GPIO_SWITCHES[4]  = GPIO_SWITCHES[4];
  assign \GPIO_SWITCHES[5]  = GPIO_SWITCHES[5];
  assign \GPIO_SWITCHES[6]  = GPIO_SWITCHES[6];
  assign \GPIO_SWITCHES[7]  = GPIO_SWITCHES[7];
  assign \GPIO_SWITCHES[8]  = GPIO_SWITCHES[8];
  assign \GPIO_SWITCHES[9]  = GPIO_SWITCHES[9];
  assign \RXD[0]  = RXD[0];
  assign \RXD[1]  = RXD[1];
  OBUF AUDIO_EN_OBUF_inst
       (.I(1'b1),
        .O(AUDIO_EN));
  OBUF AUDIO_OBUF_inst
       (.I(1'b0),
        .O(AUDIO));
  (* box_type = "PRIMITIVE" *) 
  BUFG BUFG_INST1
       (.I(clkdv),
        .O(ETH_CLK_OBUF));
  (* box_type = "PRIMITIVE" *) 
  BUFG BUFG_INST2
       (.I(clk0),
        .O(CLKFB));
  CHARSVGA CHARSVGA_INST_1
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .HSYNCH(HSYNCH_OBUF),
        .INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
        .VGA_B_OBUF(VGA_B_OBUF),
        .VSYNCH(VSYNCH_OBUF));
  OBUF ETH_CLK_OBUF_inst
       (.I(ETH_CLK_OBUF),
        .O(ETH_CLK));
  (* OPT_INSERTED *) 
  IBUF \GPIO_BUTTONS[0]_IBUF_inst 
       (.I(\GPIO_BUTTONS[0] ),
        .O(\GPIO_BUTTONS[0]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_BUTTONS[1]_IBUF_inst 
       (.I(\GPIO_BUTTONS[1] ),
        .O(\GPIO_BUTTONS[1]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_BUTTONS[2]_IBUF_inst 
       (.I(\GPIO_BUTTONS[2] ),
        .O(\GPIO_BUTTONS[2]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_BUTTONS[3]_IBUF_inst 
       (.I(\GPIO_BUTTONS[3] ),
        .O(\GPIO_BUTTONS[3]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_BUTTONS[4]_IBUF_inst 
       (.I(\GPIO_BUTTONS[4] ),
        .O(\GPIO_BUTTONS[4]_IBUF ));
  OBUF \GPIO_LEDS_OBUF[0]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[0]));
  OBUF \GPIO_LEDS_OBUF[10]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[10]));
  OBUF \GPIO_LEDS_OBUF[11]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[11]));
  OBUF \GPIO_LEDS_OBUF[12]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[12]));
  OBUF \GPIO_LEDS_OBUF[13]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[13]));
  OBUF \GPIO_LEDS_OBUF[14]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[14]));
  OBUF \GPIO_LEDS_OBUF[15]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[15]));
  OBUF \GPIO_LEDS_OBUF[1]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[1]));
  OBUF \GPIO_LEDS_OBUF[2]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[2]));
  OBUF \GPIO_LEDS_OBUF[3]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[3]));
  OBUF \GPIO_LEDS_OBUF[4]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[4]));
  OBUF \GPIO_LEDS_OBUF[5]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[5]));
  OBUF \GPIO_LEDS_OBUF[6]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[6]));
  OBUF \GPIO_LEDS_OBUF[7]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[7]));
  OBUF \GPIO_LEDS_OBUF[8]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[8]));
  OBUF \GPIO_LEDS_OBUF[9]_inst 
       (.I(1'b0),
        .O(GPIO_LEDS[9]));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[0]_IBUF_inst 
       (.I(\GPIO_SWITCHES[0] ),
        .O(\GPIO_SWITCHES[0]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[10]_IBUF_inst 
       (.I(\GPIO_SWITCHES[10] ),
        .O(\GPIO_SWITCHES[10]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[11]_IBUF_inst 
       (.I(\GPIO_SWITCHES[11] ),
        .O(\GPIO_SWITCHES[11]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[12]_IBUF_inst 
       (.I(\GPIO_SWITCHES[12] ),
        .O(\GPIO_SWITCHES[12]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[13]_IBUF_inst 
       (.I(\GPIO_SWITCHES[13] ),
        .O(\GPIO_SWITCHES[13]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[14]_IBUF_inst 
       (.I(\GPIO_SWITCHES[14] ),
        .O(\GPIO_SWITCHES[14]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[15]_IBUF_inst 
       (.I(\GPIO_SWITCHES[15] ),
        .O(\GPIO_SWITCHES[15]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[1]_IBUF_inst 
       (.I(\GPIO_SWITCHES[1] ),
        .O(\GPIO_SWITCHES[1]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[2]_IBUF_inst 
       (.I(\GPIO_SWITCHES[2] ),
        .O(\GPIO_SWITCHES[2]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[3]_IBUF_inst 
       (.I(\GPIO_SWITCHES[3] ),
        .O(\GPIO_SWITCHES[3]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[4]_IBUF_inst 
       (.I(\GPIO_SWITCHES[4] ),
        .O(\GPIO_SWITCHES[4]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[5]_IBUF_inst 
       (.I(\GPIO_SWITCHES[5] ),
        .O(\GPIO_SWITCHES[5]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[6]_IBUF_inst 
       (.I(\GPIO_SWITCHES[6] ),
        .O(\GPIO_SWITCHES[6]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[7]_IBUF_inst 
       (.I(\GPIO_SWITCHES[7] ),
        .O(\GPIO_SWITCHES[7]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[8]_IBUF_inst 
       (.I(\GPIO_SWITCHES[8] ),
        .O(\GPIO_SWITCHES[8]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \GPIO_SWITCHES[9]_IBUF_inst 
       (.I(\GPIO_SWITCHES[9] ),
        .O(\GPIO_SWITCHES[9]_IBUF ));
  OBUF HSYNCH_OBUF_inst
       (.I(HSYNCH_OBUF),
        .O(HSYNCH));
  I2C I2C_INST_1
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
        .SCL_IBUF(SCL_IBUF),
        .SCL_TRI(SCL_TRI),
        .SDA_IBUF(SDA_IBUF),
        .SDA_TRI(SDA_TRI));
  FDRE INTERNAL_RST_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(NOT_LOCKED),
        .Q(INTERNAL_RST_reg_n_0),
        .R(1'b0));
  OBUF \JC_OBUF[0]_inst 
       (.I(1'b1),
        .O(JC[0]));
  OBUF \JC_OBUF[1]_inst 
       (.I(JC_IBUF),
        .O(JC[1]));
  (* OPT_INSERTED *) 
  IBUF KC_IBUF_inst
       (.I(KC),
        .O(KC_IBUF));
  (* OPT_INSERTED *) 
  IBUF KD_IBUF_inst
       (.I(KD),
        .O(KD_IBUF));
  OBUF LED_B_PWM_OBUF_inst
       (.I(LED_B_PWM_OBUF),
        .O(LED_B_PWM));
  OBUF LED_G_PWM_OBUF_inst
       (.I(LED_G_PWM_OBUF),
        .O(LED_G_PWM));
  OBUF LED_R_PWM_OBUF_inst
       (.I(LED_R_PWM_OBUF),
        .O(LED_R_PWM));
  LUT1 #(
    .INIT(2'h1)) 
    NOT_LOCKED_i_1
       (.I0(locked_internal),
        .O(NOT_LOCKED_i_1_n_0));
  FDRE NOT_LOCKED_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(NOT_LOCKED_i_1_n_0),
        .Q(NOT_LOCKED),
        .R(1'b0));
  OBUF PHY_RESET_N_OBUF_inst
       (.I(PHY_RESET_N_OBUF),
        .O(PHY_RESET_N));
  LUT1 #(
    .INIT(2'h1)) 
    PHY_RESET_N_OBUF_inst_i_1
       (.I0(INTERNAL_RST_reg_n_0),
        .O(PHY_RESET_N_OBUF));
  PWM PWM_INST_1
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .LED_R_PWM_OBUF(LED_R_PWM_OBUF));
  PWM_0 PWM_INST_2
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .LED_G_PWM_OBUF(LED_G_PWM_OBUF));
  PWM_1 PWM_INST_3
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .LED_B_PWM_OBUF(LED_B_PWM_OBUF));
  IBUF RS232_RX_IBUF_inst
       (.I(RS232_RX),
        .O(RS232_RX_IBUF));
  OBUF RS232_TX_OBUF_inst
       (.I(RS232_TX_OBUF),
        .O(RS232_TX));
  IBUF RST_IBUF_inst
       (.I(RST),
        .O(RST_IBUF));
  (* OPT_INSERTED *) 
  IBUF RXDV_IBUF_inst
       (.I(RXDV),
        .O(RXDV_IBUF));
  (* OPT_INSERTED *) 
  IBUF \RXD[0]_IBUF_inst 
       (.I(\RXD[0] ),
        .O(\RXD[0]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF \RXD[1]_IBUF_inst 
       (.I(\RXD[1] ),
        .O(\RXD[1]_IBUF ));
  (* OPT_INSERTED *) 
  IBUF RXER_IBUF_inst
       (.I(RXER),
        .O(RXER_IBUF));
  IOBUF_HD3 SCL_IOBUF_inst
       (.I(1'b0),
        .IO(SCL),
        .O(SCL_IBUF),
        .T(SCL_TRI));
  IOBUF_UNIQ_BASE_ SDA_IOBUF_inst
       (.I(1'b0),
        .IO(SDA),
        .O(SDA_IBUF),
        .T(SDA_TRI));
  SERIAL_INPUT SERIAL_INPUT_INST_1
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
        .OUT1(OUT1),
        .OUT1_ACK(OUT1_ACK),
        .OUT1_STB(OUT1_STB),
        .RX(RS232_RX_IBUF));
  serial_output SERIAL_OUTPUT_INST_1
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .IN1_ACK(IN1_ACK),
        .IN1_STB(IN1_STB),
        .INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
        .Q({USER_DESIGN_INST_1_n_2,USER_DESIGN_INST_1_n_3,USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8,USER_DESIGN_INST_1_n_9}),
        .RS232_TX_OBUF(RS232_TX_OBUF));
  OBUF \SEVEN_SEGMENT_ANNODE_OBUF[0]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_ANNODE[0]));
  OBUF \SEVEN_SEGMENT_ANNODE_OBUF[1]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_ANNODE[1]));
  OBUF \SEVEN_SEGMENT_ANNODE_OBUF[2]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_ANNODE[2]));
  OBUF \SEVEN_SEGMENT_ANNODE_OBUF[3]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_ANNODE[3]));
  OBUF \SEVEN_SEGMENT_ANNODE_OBUF[4]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_ANNODE[4]));
  OBUF \SEVEN_SEGMENT_ANNODE_OBUF[5]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_ANNODE[5]));
  OBUF \SEVEN_SEGMENT_ANNODE_OBUF[6]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_ANNODE[6]));
  OBUF \SEVEN_SEGMENT_ANNODE_OBUF[7]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_ANNODE[7]));
  OBUF \SEVEN_SEGMENT_CATHODE_OBUF[0]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_CATHODE[0]));
  OBUF \SEVEN_SEGMENT_CATHODE_OBUF[1]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_CATHODE[1]));
  OBUF \SEVEN_SEGMENT_CATHODE_OBUF[2]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_CATHODE[2]));
  OBUF \SEVEN_SEGMENT_CATHODE_OBUF[3]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_CATHODE[3]));
  OBUF \SEVEN_SEGMENT_CATHODE_OBUF[4]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_CATHODE[4]));
  OBUF \SEVEN_SEGMENT_CATHODE_OBUF[5]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_CATHODE[5]));
  OBUF \SEVEN_SEGMENT_CATHODE_OBUF[6]_inst 
       (.I(1'b1),
        .O(SEVEN_SEGMENT_CATHODE[6]));
  OBUF \TXD_OBUF[0]_inst 
       (.I(TXD_OBUF[0]),
        .O(TXD[0]));
  OBUF \TXD_OBUF[1]_inst 
       (.I(TXD_OBUF[1]),
        .O(TXD[1]));
  OBUF TXEN_OBUF_inst
       (.I(TXEN_OBUF),
        .O(TXEN));
  user_design USER_DESIGN_INST_1
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .IN1_ACK(IN1_ACK),
        .IN1_STB(IN1_STB),
        .INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
        .OUT1(OUT1),
        .OUT1_ACK(OUT1_ACK),
        .OUT1_STB(OUT1_STB),
        .output_rs232_out({USER_DESIGN_INST_1_n_2,USER_DESIGN_INST_1_n_3,USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8,USER_DESIGN_INST_1_n_9}));
  OBUF \VGA_B_OBUF[0]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_B[0]));
  OBUF \VGA_B_OBUF[1]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_B[1]));
  OBUF \VGA_B_OBUF[2]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_B[2]));
  OBUF \VGA_B_OBUF[3]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_B[3]));
  OBUF \VGA_G_OBUF[0]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_G[0]));
  OBUF \VGA_G_OBUF[1]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_G[1]));
  OBUF \VGA_G_OBUF[2]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_G[2]));
  OBUF \VGA_G_OBUF[3]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_G[3]));
  OBUF \VGA_R_OBUF[0]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_R[0]));
  OBUF \VGA_R_OBUF[1]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_R[1]));
  OBUF \VGA_R_OBUF[2]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_R[2]));
  OBUF \VGA_R_OBUF[3]_inst 
       (.I(VGA_B_OBUF),
        .O(VGA_R[3]));
  OBUF VSYNCH_OBUF_inst
       (.I(VSYNCH_OBUF),
        .O(VSYNCH));
  (* CAPACITANCE = "DONT_CARE" *) 
  (* IBUF_DELAY_VALUE = "0" *) 
  (* XILINX_LEGACY_PRIM = "IBUFG" *) 
  (* box_type = "PRIMITIVE" *) 
  IBUF #(
    .IOSTANDARD("DEFAULT")) 
    clkin1_buf
       (.I(CLK_IN),
        .O(CLKIN));
  (* XILINX_LEGACY_PRIM = "DCM_SP" *) 
  (* XILINX_TRANSFORM_PINMAP = "STATUS[7]:DO[7] STATUS[6]:DO[6] STATUS[5]:DO[5] STATUS[4]:DO[4] STATUS[3]:DO[3] STATUS[2]:DO[2] STATUS[1]:DO[1] STATUS[0]:DO[0] CLKIN:CLKIN1 CLKFX:CLKOUT0 CLKFX180:CLKOUT0B CLK2X:CLKOUT1 CLK2X180:CLKOUT1B CLK90:CLKOUT2 CLK270:CLKOUT2B CLKDV:CLKOUT4 CLK0:CLKFBOUT CLK180:CLKFBOUTB CLKFB:CLKFBIN" *) 
  (* box_type = "PRIMITIVE" *) 
  MMCME2_ADV #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKFBOUT_MULT_F(8.000000),
    .CLKFBOUT_PHASE(0.000000),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
    .CLKIN1_PERIOD(10.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE_F(2.000000),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT0_USE_FINE_PS("FALSE"),
    .CLKOUT1_DIVIDE(4),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT1_USE_FINE_PS("FALSE"),
    .CLKOUT2_DIVIDE(8),
    .CLKOUT2_DUTY_CYCLE(0.500000),
    .CLKOUT2_PHASE(90.000000),
    .CLKOUT2_USE_FINE_PS("FALSE"),
    .CLKOUT3_DIVIDE(8),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT3_USE_FINE_PS("FALSE"),
    .CLKOUT4_CASCADE("FALSE"),
    .CLKOUT4_DIVIDE(16),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(0.000000),
    .CLKOUT4_USE_FINE_PS("FALSE"),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .CLKOUT5_USE_FINE_PS("FALSE"),
    .CLKOUT6_DIVIDE(1),
    .CLKOUT6_DUTY_CYCLE(0.500000),
    .CLKOUT6_PHASE(0.000000),
    .CLKOUT6_USE_FINE_PS("FALSE"),
    .COMPENSATION("ZHOLD"),
    .DIVCLK_DIVIDE(1),
    .IS_PSINCDEC_INVERTED(1'b1),
    .IS_RST_INVERTED(1'b1),
    .REF_JITTER1(0.010000),
    .REF_JITTER2(0.010000),
    .STARTUP_WAIT("FALSE")) 
    dcm_sp_inst
       (.CLKFBIN(CLKFB),
        .CLKFBOUT(clk0),
        .CLKFBOUTB(NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED),
        .CLKFBSTOPPED(NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED),
        .CLKIN1(CLKIN),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKINSTOPPED(NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED),
        .CLKOUT0(NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED),
        .CLKOUT0B(NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED),
        .CLKOUT1(NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED),
        .CLKOUT1B(NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED),
        .CLKOUT2(NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED),
        .CLKOUT2B(NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED),
        .CLKOUT3(NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED),
        .CLKOUT3B(NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED),
        .CLKOUT4(clkdv),
        .CLKOUT5(NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED),
        .CLKOUT6(NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(NLW_dcm_sp_inst_DO_UNCONNECTED[15:0]),
        .DRDY(NLW_dcm_sp_inst_DRDY_UNCONNECTED),
        .DWE(1'b0),
        .LOCKED(locked_internal),
        .PSCLK(1'b0),
        .PSDONE(NLW_dcm_sp_inst_PSDONE_UNCONNECTED),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PWRDWN(1'b0),
        .RST(RST_IBUF));
  rmii_ethernet ethernet_inst_1
       (.D(NLW_ethernet_inst_1_D_UNCONNECTED[1:0]),
        .ETH_CLK_OBUF(ETH_CLK_OBUF),
        .INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
        .RXDV_IBUF(NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED),
        .RXER_IBUF(NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED),
        .TXD_OBUF(TXD_OBUF),
        .TXEN_OBUF(TXEN_OBUF));
  pwm_audio pwm_audio_inst_1
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
        .JC_IBUF(JC_IBUF));
endmodule

module CHARSVGA
   (HSYNCH,
    VSYNCH,
    VGA_B_OBUF,
    ETH_CLK_OBUF,
    INTERNAL_RST_reg);
  output HSYNCH;
  output VSYNCH;
  output [0:0]VGA_B_OBUF;
  input ETH_CLK_OBUF;
  input INTERNAL_RST_reg;

  wire [12:1]AOUT;
  wire BLANK;
  wire BLANK_DEL;
  wire BLANK_DEL_DEL;
  wire [3:0]DOUT;
  wire ETH_CLK_OBUF;
  wire HSYNCH;
  wire HSYNCH_DEL;
  wire INTERNAL_RST_reg;
  wire [2:0]PIXCOL_DEL;
  wire \PIXCOL_DEL_DEL_reg_n_0_[0] ;
  wire \PIXCOL_DEL_DEL_reg_n_0_[1] ;
  wire \PIXCOL_DEL_DEL_reg_n_0_[2] ;
  wire [7:0]PIXELS_reg__0;
  wire TIMEING1_n_0;
  wire TIMEING1_n_1;
  wire TIMEING1_n_15;
  wire TIMEING1_n_16;
  wire TIMEING1_n_17;
  wire TIMEING1_n_18;
  wire TIMEING1_n_19;
  wire TIMEING1_n_2;
  wire TIMEING1_n_20;
  wire [0:0]VGA_B_OBUF;
  wire \VGA_R_OBUF[3]_inst_i_2_n_0 ;
  wire \VGA_R_OBUF[3]_inst_i_3_n_0 ;
  wire VSYNCH;
  wire VSYNCH_DEL;
  wire [2:0]sel;
  wire NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED;
  wire NLW_PIXELS_reg_REGCEB_UNCONNECTED;
  wire [15:8]NLW_PIXELS_reg_DOADO_UNCONNECTED;
  wire [15:0]NLW_PIXELS_reg_DOBDO_UNCONNECTED;
  wire [1:0]NLW_PIXELS_reg_DOPADOP_UNCONNECTED;
  wire [1:0]NLW_PIXELS_reg_DOPBDOP_UNCONNECTED;

  FDRE BLANK_DEL_DEL_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BLANK_DEL),
        .Q(BLANK_DEL_DEL),
        .R(1'b0));
  FDRE BLANK_DEL_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BLANK),
        .Q(BLANK_DEL),
        .R(1'b0));
  BRAM BRAM_INST_1
       (.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
        .DOBDO(DOUT),
        .ETH_CLK_OBUF(ETH_CLK_OBUF),
        .pwropt(BLANK));
  FDRE HSYNCH_DEL_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMEING1_n_19),
        .Q(HSYNCH_DEL),
        .R(1'b0));
  FDRE HSYNCH_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HSYNCH_DEL),
        .Q(HSYNCH),
        .R(1'b0));
  FDRE \PIXCOL_DEL_DEL_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(PIXCOL_DEL[0]),
        .Q(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \PIXCOL_DEL_DEL_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(PIXCOL_DEL[1]),
        .Q(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \PIXCOL_DEL_DEL_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(PIXCOL_DEL[2]),
        .Q(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \PIXCOL_DEL_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMEING1_n_0),
        .Q(PIXCOL_DEL[0]),
        .R(1'b0));
  FDRE \PIXCOL_DEL_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMEING1_n_1),
        .Q(PIXCOL_DEL[1]),
        .R(1'b0));
  FDRE \PIXCOL_DEL_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMEING1_n_2),
        .Q(PIXCOL_DEL[2]),
        .R(1'b0));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENARDEN=NEW" *) 
  (* RTL_RAM_BITS = "16384" *) 
  (* RTL_RAM_NAME = "PIXELS" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "2047" *) 
  (* bram_slice_begin = "0" *) 
  (* bram_slice_end = "17" *) 
  RAMB18E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
    .INIT_09(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
    .INIT_0A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
    .INIT_0B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
    .INIT_0C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
    .INIT_0D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
    .INIT_0E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
    .INIT_0F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
    .INIT_10(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
    .INIT_11(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
    .INIT_12(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
    .INIT_13(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
    .INIT_14(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
    .INIT_15(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
    .INIT_16(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
    .INIT_17(256'h00FF000000000000000000000022140800181010101010180000402010080402),
    .INIT_18(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
    .INIT_19(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
    .INIT_1A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
    .INIT_1B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
    .INIT_1C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
    .INIT_1D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
    .INIT_1E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
    .INIT_1F(256'h000000000000000000000060920C000000040808100808040008080808080808),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
    .INIT_29(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
    .INIT_2A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
    .INIT_2B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
    .INIT_2C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
    .INIT_2D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
    .INIT_2E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
    .INIT_2F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
    .INIT_30(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
    .INIT_31(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
    .INIT_32(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
    .INIT_33(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
    .INIT_34(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
    .INIT_35(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
    .INIT_36(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
    .INIT_37(256'h00FF000000000000000000000022140800181010101010180000402010080402),
    .INIT_38(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
    .INIT_39(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
    .INIT_3A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
    .INIT_3B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
    .INIT_3C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
    .INIT_3D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
    .INIT_3E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
    .INIT_3F(256'h000000000000000000000060920C000000040808100808040008080808080808),
    .INIT_A(18'h00000),
    .INIT_B(18'h00000),
    .IS_ENARDEN_INVERTED(1'b1),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(9),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(18'h00000),
    .SRVAL_B(18'h00000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(9),
    .WRITE_WIDTH_B(0)) 
    PIXELS_reg
       (.ADDRARDADDR({DOUT,DOUT,sel,1'b0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1}),
        .DOADO({NLW_PIXELS_reg_DOADO_UNCONNECTED[15:8],PIXELS_reg__0}),
        .DOBDO(NLW_PIXELS_reg_DOBDO_UNCONNECTED[15:0]),
        .DOPADOP(NLW_PIXELS_reg_DOPADOP_UNCONNECTED[1:0]),
        .DOPBDOP(NLW_PIXELS_reg_DOPBDOP_UNCONNECTED[1:0]),
        .ENARDEN(BLANK_DEL),
        .ENBWREN(1'b0),
        .REGCEAREGCE(NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_PIXELS_reg_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .WEA({1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0}));
  FDRE \PIXROW_DEL_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMEING1_n_16),
        .Q(sel[0]),
        .R(1'b0));
  FDRE \PIXROW_DEL_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMEING1_n_17),
        .Q(sel[1]),
        .R(1'b0));
  FDRE \PIXROW_DEL_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMEING1_n_18),
        .Q(sel[2]),
        .R(1'b0));
  VIDEO_TIME_GEN TIMEING1
       (.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
        .BLANK(BLANK),
        .D(TIMEING1_n_18),
        .ETH_CLK_OBUF(ETH_CLK_OBUF),
        .HSYNCH_DEL_reg(TIMEING1_n_19),
        .INTERNAL_RST_reg(INTERNAL_RST_reg),
        .\PIXCOL_DEL_reg[0] (TIMEING1_n_0),
        .\PIXCOL_DEL_reg[1] (TIMEING1_n_1),
        .\PIXCOL_DEL_reg[2] (TIMEING1_n_2),
        .\PIXROW_DEL_reg[0] (TIMEING1_n_16),
        .\PIXROW_DEL_reg[1] (TIMEING1_n_17),
        .VSYNCH_DEL_reg(TIMEING1_n_20));
  LUT4 #(
    .INIT(16'h00E2)) 
    \VGA_R_OBUF[3]_inst_i_1 
       (.I0(\VGA_R_OBUF[3]_inst_i_2_n_0 ),
        .I1(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
        .I2(\VGA_R_OBUF[3]_inst_i_3_n_0 ),
        .I3(BLANK_DEL_DEL),
        .O(VGA_B_OBUF));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \VGA_R_OBUF[3]_inst_i_2 
       (.I0(PIXELS_reg__0[3]),
        .I1(PIXELS_reg__0[2]),
        .I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
        .I3(PIXELS_reg__0[1]),
        .I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
        .I5(PIXELS_reg__0[0]),
        .O(\VGA_R_OBUF[3]_inst_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \VGA_R_OBUF[3]_inst_i_3 
       (.I0(PIXELS_reg__0[7]),
        .I1(PIXELS_reg__0[6]),
        .I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
        .I3(PIXELS_reg__0[5]),
        .I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
        .I5(PIXELS_reg__0[4]),
        .O(\VGA_R_OBUF[3]_inst_i_3_n_0 ));
  FDRE VSYNCH_DEL_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMEING1_n_20),
        .Q(VSYNCH_DEL),
        .R(1'b0));
  FDRE VSYNCH_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(VSYNCH_DEL),
        .Q(VSYNCH),
        .R(1'b0));
endmodule

module I2C
   (SDA_TRI,
    SCL_TRI,
    ETH_CLK_OBUF,
    SCL_IBUF,
    INTERNAL_RST_reg,
    SDA_IBUF);
  output SDA_TRI;
  output SCL_TRI;
  input ETH_CLK_OBUF;
  input SCL_IBUF;
  input INTERNAL_RST_reg;
  input SDA_IBUF;

  wire BIT_i_1_n_0;
  wire BIT_i_2_n_0;
  wire BIT_i_3_n_0;
  wire BIT_reg_n_0;
  wire [2:0]COUNT;
  wire \COUNT[0]_i_1__0_n_0 ;
  wire \COUNT[1]_i_1__0_n_0 ;
  wire \COUNT[2]_i_1_n_0 ;
  wire \COUNT[2]_i_2_n_0 ;
  wire ETH_CLK_OBUF;
  wire [3:0]GET_BIT_RETURN;
  wire \GET_BIT_RETURN[0]_i_1_n_0 ;
  wire \GET_BIT_RETURN[3]_i_1_n_0 ;
  wire INTERNAL_RST_reg;
  wire SCL_IBUF;
  wire SCL_I_D;
  wire SCL_I_SYNCH;
  wire SCL_O_i_1_n_0;
  wire SCL_O_i_2_n_0;
  wire SCL_O_i_3_n_0;
  wire SCL_O_i_4_n_0;
  wire SCL_TRI;
  wire SDA_IBUF;
  wire SDA_I_D;
  wire SDA_I_SYNCH;
  wire SDA_O_i_1_n_0;
  wire SDA_O_i_2_n_0;
  wire SDA_TRI;
  wire [3:0]SEND_BIT_RETURN;
  wire \SEND_BIT_RETURN[0]_i_1_n_0 ;
  wire \SEND_BIT_RETURN[3]_i_1_n_0 ;
  wire STARTED;
  wire STARTED_i_1_n_0;
  wire STARTED_i_2_n_0;
  wire \STATE[0]_i_2_n_0 ;
  wire \STATE[0]_i_3_n_0 ;
  wire \STATE[1]_i_1_n_0 ;
  wire \STATE[1]_i_2_n_0 ;
  wire \STATE[1]_i_3_n_0 ;
  wire \STATE[1]_i_4_n_0 ;
  wire \STATE[2]_i_1_n_0 ;
  wire \STATE[3]_i_2_n_0 ;
  wire \STATE[3]_i_3_n_0 ;
  wire \STATE[4]_i_1_n_0 ;
  wire \STATE[4]_i_2_n_0 ;
  wire \STATE[4]_i_3_n_0 ;
  wire \STATE[4]_i_4_n_0 ;
  wire \STATE[4]_i_5_n_0 ;
  wire \STATE[4]_i_6_n_0 ;
  wire \STATE_reg[0]_i_1_n_0 ;
  wire \STATE_reg[3]_i_1_n_0 ;
  wire \STATE_reg_n_0_[0] ;
  wire \STATE_reg_n_0_[1] ;
  wire \STATE_reg_n_0_[2] ;
  wire \STATE_reg_n_0_[3] ;
  wire \STATE_reg_n_0_[4] ;
  wire S_I2C_IN_ACK_i_1_n_0;
  wire S_I2C_IN_ACK_reg_n_0;
  wire S_I2C_OUT_STB_i_1_n_0;
  wire S_I2C_OUT_STB_reg_n_0;
  wire \TIMER[0]_i_1_n_0 ;
  wire \TIMER[0]_i_2_n_0 ;
  wire \TIMER[0]_i_3_n_0 ;
  wire \TIMER[10]_i_1_n_0 ;
  wire \TIMER[10]_i_2_n_0 ;
  wire \TIMER[10]_i_3_n_0 ;
  wire \TIMER[10]_i_5_n_0 ;
  wire \TIMER[10]_i_6_n_0 ;
  wire \TIMER[10]_i_7_n_0 ;
  wire \TIMER[11]_i_1_n_0 ;
  wire \TIMER[1]_i_1__2_n_0 ;
  wire \TIMER[2]_i_1_n_0 ;
  wire \TIMER[3]_i_1__2_n_0 ;
  wire \TIMER[4]_i_1__2_n_0 ;
  wire \TIMER[4]_i_3_n_0 ;
  wire \TIMER[4]_i_4_n_0 ;
  wire \TIMER[4]_i_5_n_0 ;
  wire \TIMER[4]_i_6_n_0 ;
  wire \TIMER[5]_i_1__2_n_0 ;
  wire \TIMER[5]_i_3_n_0 ;
  wire \TIMER[5]_i_4_n_0 ;
  wire \TIMER[5]_i_5_n_0 ;
  wire \TIMER[5]_i_6_n_0 ;
  wire \TIMER[6]_i_1_n_0 ;
  wire \TIMER[7]_i_1_n_0 ;
  wire \TIMER[8]_i_1_n_0 ;
  wire \TIMER[9]_i_1__2_n_0 ;
  wire \TIMER_reg[10]_i_4_n_5 ;
  wire \TIMER_reg[10]_i_4_n_6 ;
  wire \TIMER_reg[10]_i_4_n_7 ;
  wire \TIMER_reg[4]_i_2_n_0 ;
  wire \TIMER_reg[4]_i_2_n_4 ;
  wire \TIMER_reg[4]_i_2_n_5 ;
  wire \TIMER_reg[4]_i_2_n_6 ;
  wire \TIMER_reg[4]_i_2_n_7 ;
  wire \TIMER_reg[5]_i_2_n_0 ;
  wire \TIMER_reg[5]_i_2_n_4 ;
  wire \TIMER_reg[5]_i_2_n_5 ;
  wire \TIMER_reg[5]_i_2_n_6 ;
  wire \TIMER_reg[5]_i_2_n_7 ;
  wire \TIMER_reg_n_0_[0] ;
  wire \TIMER_reg_n_0_[10] ;
  wire \TIMER_reg_n_0_[11] ;
  wire \TIMER_reg_n_0_[1] ;
  wire \TIMER_reg_n_0_[2] ;
  wire \TIMER_reg_n_0_[3] ;
  wire \TIMER_reg_n_0_[4] ;
  wire \TIMER_reg_n_0_[5] ;
  wire \TIMER_reg_n_0_[6] ;
  wire \TIMER_reg_n_0_[7] ;
  wire \TIMER_reg_n_0_[8] ;
  wire \TIMER_reg_n_0_[9] ;
  wire g0_b0_n_0;
  wire [3:0]\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED ;
  wire [3:3]\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED ;
  wire [2:0]\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED ;
  wire [2:0]\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hFFF0FA3300000A00)) 
    BIT_i_1
       (.I0(SDA_I_SYNCH),
        .I1(BIT_i_2_n_0),
        .I2(BIT_i_3_n_0),
        .I3(\STATE_reg_n_0_[4] ),
        .I4(\STATE_reg_n_0_[2] ),
        .I5(BIT_reg_n_0),
        .O(BIT_i_1_n_0));
  LUT3 #(
    .INIT(8'h40)) 
    BIT_i_2
       (.I0(\STATE_reg_n_0_[1] ),
        .I1(\STATE_reg_n_0_[0] ),
        .I2(\STATE_reg_n_0_[3] ),
        .O(BIT_i_2_n_0));
  LUT3 #(
    .INIT(8'hEF)) 
    BIT_i_3
       (.I0(\STATE_reg_n_0_[0] ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[1] ),
        .O(BIT_i_3_n_0));
  FDRE BIT_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BIT_i_1_n_0),
        .Q(BIT_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'h1FF0)) 
    \COUNT[0]_i_1__0 
       (.I0(\STATE_reg_n_0_[2] ),
        .I1(\STATE_reg_n_0_[1] ),
        .I2(\COUNT[2]_i_2_n_0 ),
        .I3(COUNT[0]),
        .O(\COUNT[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'hF1FF1F00)) 
    \COUNT[1]_i_1__0 
       (.I0(\STATE_reg_n_0_[1] ),
        .I1(\STATE_reg_n_0_[2] ),
        .I2(COUNT[0]),
        .I3(\COUNT[2]_i_2_n_0 ),
        .I4(COUNT[1]),
        .O(\COUNT[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF1FFFF111F0000)) 
    \COUNT[2]_i_1 
       (.I0(\STATE_reg_n_0_[2] ),
        .I1(\STATE_reg_n_0_[1] ),
        .I2(COUNT[0]),
        .I3(COUNT[1]),
        .I4(\COUNT[2]_i_2_n_0 ),
        .I5(COUNT[2]),
        .O(\COUNT[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00100401)) 
    \COUNT[2]_i_2 
       (.I0(\STATE_reg_n_0_[4] ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[2] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(\STATE_reg_n_0_[0] ),
        .O(\COUNT[2]_i_2_n_0 ));
  FDRE \COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\COUNT[0]_i_1__0_n_0 ),
        .Q(COUNT[0]),
        .R(1'b0));
  FDRE \COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\COUNT[1]_i_1__0_n_0 ),
        .Q(COUNT[1]),
        .R(1'b0));
  FDRE \COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\COUNT[2]_i_1_n_0 ),
        .Q(COUNT[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFBFFFFFF00000010)) 
    \GET_BIT_RETURN[0]_i_1 
       (.I0(\STATE_reg_n_0_[4] ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[2] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(\STATE_reg_n_0_[0] ),
        .I5(GET_BIT_RETURN[0]),
        .O(\GET_BIT_RETURN[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFEF04000000)) 
    \GET_BIT_RETURN[3]_i_1 
       (.I0(\STATE_reg_n_0_[4] ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[2] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(\STATE_reg_n_0_[0] ),
        .I5(GET_BIT_RETURN[3]),
        .O(\GET_BIT_RETURN[3]_i_1_n_0 ));
  FDRE \GET_BIT_RETURN_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\GET_BIT_RETURN[0]_i_1_n_0 ),
        .Q(GET_BIT_RETURN[0]),
        .R(1'b0));
  FDRE \GET_BIT_RETURN_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\GET_BIT_RETURN[3]_i_1_n_0 ),
        .Q(GET_BIT_RETURN[3]),
        .R(1'b0));
  FDRE SCL_I_D_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(SCL_IBUF),
        .Q(SCL_I_D),
        .R(1'b0));
  FDRE SCL_I_SYNCH_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(SCL_I_D),
        .Q(SCL_I_SYNCH),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h403FFFFF403F0000)) 
    SCL_O_i_1
       (.I0(\STATE_reg_n_0_[0] ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[2] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(SCL_O_i_2_n_0),
        .I5(SCL_TRI),
        .O(SCL_O_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF01000000)) 
    SCL_O_i_2
       (.I0(\TIMER[0]_i_2_n_0 ),
        .I1(SCL_O_i_3_n_0),
        .I2(\TIMER_reg_n_0_[0] ),
        .I3(\STATE_reg_n_0_[2] ),
        .I4(\STATE_reg_n_0_[0] ),
        .I5(SCL_O_i_4_n_0),
        .O(SCL_O_i_2_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    SCL_O_i_3
       (.I0(\STATE_reg_n_0_[4] ),
        .I1(\STATE_reg_n_0_[3] ),
        .O(SCL_O_i_3_n_0));
  LUT6 #(
    .INIT(64'h3C0C0C2C3C000000)) 
    SCL_O_i_4
       (.I0(\TIMER[10]_i_3_n_0 ),
        .I1(\STATE_reg_n_0_[0] ),
        .I2(\STATE_reg_n_0_[1] ),
        .I3(\STATE_reg_n_0_[2] ),
        .I4(\STATE_reg_n_0_[3] ),
        .I5(\STATE_reg_n_0_[4] ),
        .O(SCL_O_i_4_n_0));
  FDSE SCL_O_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(SCL_O_i_1_n_0),
        .Q(SCL_TRI),
        .S(INTERNAL_RST_reg));
  FDRE SDA_I_D_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(SDA_IBUF),
        .Q(SDA_I_D),
        .R(1'b0));
  FDRE SDA_I_SYNCH_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(SDA_I_D),
        .Q(SDA_I_SYNCH),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hADA5FFFFADA50000)) 
    SDA_O_i_1
       (.I0(\STATE_reg_n_0_[3] ),
        .I1(BIT_reg_n_0),
        .I2(\STATE_reg_n_0_[1] ),
        .I3(\STATE_reg_n_0_[2] ),
        .I4(SDA_O_i_2_n_0),
        .I5(SDA_TRI),
        .O(SDA_O_i_1_n_0));
  LUT6 #(
    .INIT(64'h9098803080988030)) 
    SDA_O_i_2
       (.I0(\STATE_reg_n_0_[2] ),
        .I1(\STATE_reg_n_0_[0] ),
        .I2(\STATE_reg_n_0_[4] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(\STATE_reg_n_0_[3] ),
        .I5(\TIMER[10]_i_3_n_0 ),
        .O(SDA_O_i_2_n_0));
  FDSE SDA_O_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(SDA_O_i_1_n_0),
        .Q(SDA_TRI),
        .S(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'hFFFFFFBF01000000)) 
    \SEND_BIT_RETURN[0]_i_1 
       (.I0(\STATE_reg_n_0_[4] ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[0] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(\STATE_reg_n_0_[2] ),
        .I5(SEND_BIT_RETURN[0]),
        .O(\SEND_BIT_RETURN[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFFFF00000040)) 
    \SEND_BIT_RETURN[3]_i_1 
       (.I0(\STATE_reg_n_0_[4] ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[0] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(\STATE_reg_n_0_[2] ),
        .I5(SEND_BIT_RETURN[3]),
        .O(\SEND_BIT_RETURN[3]_i_1_n_0 ));
  FDRE \SEND_BIT_RETURN_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\SEND_BIT_RETURN[0]_i_1_n_0 ),
        .Q(SEND_BIT_RETURN[0]),
        .R(1'b0));
  FDRE \SEND_BIT_RETURN_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\SEND_BIT_RETURN[3]_i_1_n_0 ),
        .Q(SEND_BIT_RETURN[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h7FFDFFFD08000000)) 
    STARTED_i_1
       (.I0(STARTED_i_2_n_0),
        .I1(\STATE_reg_n_0_[4] ),
        .I2(\STATE_reg_n_0_[3] ),
        .I3(\STATE_reg_n_0_[2] ),
        .I4(\TIMER[10]_i_3_n_0 ),
        .I5(STARTED),
        .O(STARTED_i_1_n_0));
  LUT4 #(
    .INIT(16'hEAAB)) 
    STARTED_i_2
       (.I0(\STATE_reg_n_0_[3] ),
        .I1(\STATE_reg_n_0_[1] ),
        .I2(\STATE_reg_n_0_[2] ),
        .I3(\STATE_reg_n_0_[0] ),
        .O(STARTED_i_2_n_0));
  FDRE STARTED_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(STARTED_i_1_n_0),
        .Q(STARTED),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hB0FC3CCF)) 
    \STATE[0]_i_2 
       (.I0(SEND_BIT_RETURN[0]),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[1] ),
        .I3(\STATE_reg_n_0_[0] ),
        .I4(\STATE_reg_n_0_[2] ),
        .O(\STATE[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h040004005F5F5A5F)) 
    \STATE[0]_i_3 
       (.I0(\STATE_reg_n_0_[3] ),
        .I1(STARTED),
        .I2(\STATE_reg_n_0_[2] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(GET_BIT_RETURN[0]),
        .I5(\STATE_reg_n_0_[0] ),
        .O(\STATE[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \STATE[1]_i_1 
       (.I0(\STATE[1]_i_2_n_0 ),
        .I1(\STATE[1]_i_3_n_0 ),
        .O(\STATE[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h12781258FFFFFFFF)) 
    \STATE[1]_i_2 
       (.I0(\STATE_reg_n_0_[1] ),
        .I1(\STATE_reg_n_0_[2] ),
        .I2(\STATE_reg_n_0_[0] ),
        .I3(\STATE_reg_n_0_[3] ),
        .I4(STARTED),
        .I5(\STATE_reg_n_0_[4] ),
        .O(\STATE[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0005010555155055)) 
    \STATE[1]_i_3 
       (.I0(\STATE_reg_n_0_[4] ),
        .I1(\STATE[1]_i_4_n_0 ),
        .I2(\STATE_reg_n_0_[3] ),
        .I3(\STATE_reg_n_0_[0] ),
        .I4(\STATE_reg_n_0_[1] ),
        .I5(\STATE_reg_n_0_[2] ),
        .O(\STATE[1]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \STATE[1]_i_4 
       (.I0(COUNT[2]),
        .I1(COUNT[1]),
        .I2(COUNT[0]),
        .O(\STATE[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h406EB828406E3828)) 
    \STATE[2]_i_1 
       (.I0(\STATE_reg_n_0_[2] ),
        .I1(\STATE_reg_n_0_[1] ),
        .I2(\STATE_reg_n_0_[0] ),
        .I3(\STATE_reg_n_0_[3] ),
        .I4(\STATE_reg_n_0_[4] ),
        .I5(SEND_BIT_RETURN[0]),
        .O(\STATE[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8F00F5F0)) 
    \STATE[3]_i_2 
       (.I0(\STATE_reg_n_0_[2] ),
        .I1(SEND_BIT_RETURN[3]),
        .I2(\STATE_reg_n_0_[1] ),
        .I3(\STATE_reg_n_0_[3] ),
        .I4(\STATE_reg_n_0_[0] ),
        .O(\STATE[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0F0F0200)) 
    \STATE[3]_i_3 
       (.I0(GET_BIT_RETURN[3]),
        .I1(\STATE_reg_n_0_[0] ),
        .I2(\STATE_reg_n_0_[2] ),
        .I3(\STATE_reg_n_0_[1] ),
        .I4(\STATE_reg_n_0_[3] ),
        .O(\STATE[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF4F4F0FF)) 
    \STATE[4]_i_1 
       (.I0(\STATE[4]_i_3_n_0 ),
        .I1(\STATE_reg_n_0_[0] ),
        .I2(\STATE[4]_i_4_n_0 ),
        .I3(\STATE[4]_i_5_n_0 ),
        .I4(\STATE_reg_n_0_[1] ),
        .I5(\STATE[4]_i_6_n_0 ),
        .O(\STATE[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h1301FD80)) 
    \STATE[4]_i_2 
       (.I0(\STATE_reg_n_0_[1] ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[0] ),
        .I3(\STATE_reg_n_0_[4] ),
        .I4(\STATE_reg_n_0_[2] ),
        .O(\STATE[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEE0FEE00EE0F)) 
    \STATE[4]_i_3 
       (.I0(\TIMER_reg_n_0_[0] ),
        .I1(\TIMER[0]_i_2_n_0 ),
        .I2(S_I2C_OUT_STB_reg_n_0),
        .I3(\STATE_reg_n_0_[3] ),
        .I4(\STATE_reg_n_0_[4] ),
        .I5(\STATE_reg_n_0_[2] ),
        .O(\STATE[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h80AA8000)) 
    \STATE[4]_i_4 
       (.I0(\TIMER[10]_i_3_n_0 ),
        .I1(\STATE_reg_n_0_[2] ),
        .I2(\STATE_reg_n_0_[3] ),
        .I3(\STATE_reg_n_0_[0] ),
        .I4(\STATE_reg_n_0_[4] ),
        .O(\STATE[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFC0C0CDCFCFCDCDC)) 
    \STATE[4]_i_5 
       (.I0(S_I2C_IN_ACK_reg_n_0),
        .I1(\STATE_reg_n_0_[4] ),
        .I2(\STATE_reg_n_0_[0] ),
        .I3(\STATE_reg_n_0_[3] ),
        .I4(\STATE_reg_n_0_[2] ),
        .I5(SCL_I_SYNCH),
        .O(\STATE[4]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h004075BB)) 
    \STATE[4]_i_6 
       (.I0(\STATE_reg_n_0_[2] ),
        .I1(\STATE_reg_n_0_[0] ),
        .I2(SCL_I_SYNCH),
        .I3(\STATE_reg_n_0_[3] ),
        .I4(\STATE_reg_n_0_[4] ),
        .O(\STATE[4]_i_6_n_0 ));
  FDRE \STATE_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\STATE[4]_i_1_n_0 ),
        .D(\STATE_reg[0]_i_1_n_0 ),
        .Q(\STATE_reg_n_0_[0] ),
        .R(INTERNAL_RST_reg));
  MUXF7 \STATE_reg[0]_i_1 
       (.I0(\STATE[0]_i_2_n_0 ),
        .I1(\STATE[0]_i_3_n_0 ),
        .O(\STATE_reg[0]_i_1_n_0 ),
        .S(\STATE_reg_n_0_[4] ));
  FDRE \STATE_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\STATE[4]_i_1_n_0 ),
        .D(\STATE[1]_i_1_n_0 ),
        .Q(\STATE_reg_n_0_[1] ),
        .R(INTERNAL_RST_reg));
  FDRE \STATE_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\STATE[4]_i_1_n_0 ),
        .D(\STATE[2]_i_1_n_0 ),
        .Q(\STATE_reg_n_0_[2] ),
        .R(INTERNAL_RST_reg));
  FDRE \STATE_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\STATE[4]_i_1_n_0 ),
        .D(\STATE_reg[3]_i_1_n_0 ),
        .Q(\STATE_reg_n_0_[3] ),
        .R(INTERNAL_RST_reg));
  MUXF7 \STATE_reg[3]_i_1 
       (.I0(\STATE[3]_i_2_n_0 ),
        .I1(\STATE[3]_i_3_n_0 ),
        .O(\STATE_reg[3]_i_1_n_0 ),
        .S(\STATE_reg_n_0_[4] ));
  FDRE \STATE_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\STATE[4]_i_1_n_0 ),
        .D(\STATE[4]_i_2_n_0 ),
        .Q(\STATE_reg_n_0_[4] ),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'hFFFEFFFF00010000)) 
    S_I2C_IN_ACK_i_1
       (.I0(\STATE_reg_n_0_[2] ),
        .I1(\STATE_reg_n_0_[1] ),
        .I2(\STATE_reg_n_0_[3] ),
        .I3(\STATE_reg_n_0_[4] ),
        .I4(\STATE_reg_n_0_[0] ),
        .I5(S_I2C_IN_ACK_reg_n_0),
        .O(S_I2C_IN_ACK_i_1_n_0));
  FDRE S_I2C_IN_ACK_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(S_I2C_IN_ACK_i_1_n_0),
        .Q(S_I2C_IN_ACK_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFDFFFF00020000)) 
    S_I2C_OUT_STB_i_1
       (.I0(\STATE_reg_n_0_[1] ),
        .I1(\STATE_reg_n_0_[2] ),
        .I2(\STATE_reg_n_0_[3] ),
        .I3(\STATE_reg_n_0_[4] ),
        .I4(\STATE_reg_n_0_[0] ),
        .I5(S_I2C_OUT_STB_reg_n_0),
        .O(S_I2C_OUT_STB_i_1_n_0));
  FDRE S_I2C_OUT_STB_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(S_I2C_OUT_STB_i_1_n_0),
        .Q(S_I2C_OUT_STB_reg_n_0),
        .R(INTERNAL_RST_reg));
  LUT5 #(
    .INIT(32'h00FFA800)) 
    \TIMER[0]_i_1 
       (.I0(\TIMER[0]_i_2_n_0 ),
        .I1(\STATE_reg_n_0_[4] ),
        .I2(\STATE_reg_n_0_[3] ),
        .I3(g0_b0_n_0),
        .I4(\TIMER_reg_n_0_[0] ),
        .O(\TIMER[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TIMER[0]_i_2 
       (.I0(\TIMER_reg_n_0_[3] ),
        .I1(\TIMER_reg_n_0_[11] ),
        .I2(\TIMER_reg_n_0_[7] ),
        .I3(\TIMER_reg_n_0_[2] ),
        .I4(\TIMER_reg_n_0_[1] ),
        .I5(\TIMER[0]_i_3_n_0 ),
        .O(\TIMER[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TIMER[0]_i_3 
       (.I0(\TIMER_reg_n_0_[6] ),
        .I1(\TIMER_reg_n_0_[8] ),
        .I2(\TIMER_reg_n_0_[9] ),
        .I3(\TIMER_reg_n_0_[10] ),
        .I4(\TIMER_reg_n_0_[5] ),
        .I5(\TIMER_reg_n_0_[4] ),
        .O(\TIMER[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \TIMER[10]_i_1 
       (.I0(\TIMER[10]_i_3_n_0 ),
        .I1(g0_b0_n_0),
        .O(\TIMER[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \TIMER[10]_i_2 
       (.I0(\TIMER_reg[10]_i_4_n_6 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[10]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \TIMER[10]_i_3 
       (.I0(\TIMER_reg_n_0_[0] ),
        .I1(\TIMER[0]_i_2_n_0 ),
        .O(\TIMER[10]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[10]_i_5 
       (.I0(\TIMER_reg_n_0_[11] ),
        .O(\TIMER[10]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[10]_i_6 
       (.I0(\TIMER_reg_n_0_[10] ),
        .O(\TIMER[10]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[10]_i_7 
       (.I0(\TIMER_reg_n_0_[9] ),
        .O(\TIMER[10]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hAB)) 
    \TIMER[11]_i_1 
       (.I0(\TIMER_reg[10]_i_4_n_5 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \TIMER[1]_i_1__2 
       (.I0(\TIMER_reg[4]_i_2_n_7 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hAB)) 
    \TIMER[2]_i_1 
       (.I0(\TIMER_reg[4]_i_2_n_6 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \TIMER[3]_i_1__2 
       (.I0(\TIMER_reg[4]_i_2_n_5 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \TIMER[4]_i_1__2 
       (.I0(\TIMER_reg[4]_i_2_n_4 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[4]_i_1__2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[4]_i_3 
       (.I0(\TIMER_reg_n_0_[4] ),
        .O(\TIMER[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[4]_i_4 
       (.I0(\TIMER_reg_n_0_[3] ),
        .O(\TIMER[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[4]_i_5 
       (.I0(\TIMER_reg_n_0_[2] ),
        .O(\TIMER[4]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[4]_i_6 
       (.I0(\TIMER_reg_n_0_[1] ),
        .O(\TIMER[4]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \TIMER[5]_i_1__2 
       (.I0(\TIMER_reg[5]_i_2_n_7 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[5]_i_1__2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[5]_i_3 
       (.I0(\TIMER_reg_n_0_[8] ),
        .O(\TIMER[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[5]_i_4 
       (.I0(\TIMER_reg_n_0_[7] ),
        .O(\TIMER[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[5]_i_5 
       (.I0(\TIMER_reg_n_0_[6] ),
        .O(\TIMER[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[5]_i_6 
       (.I0(\TIMER_reg_n_0_[5] ),
        .O(\TIMER[5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hAB)) 
    \TIMER[6]_i_1 
       (.I0(\TIMER_reg[5]_i_2_n_6 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[6]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hAB)) 
    \TIMER[7]_i_1 
       (.I0(\TIMER_reg[5]_i_2_n_5 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hAB)) 
    \TIMER[8]_i_1 
       (.I0(\TIMER_reg[5]_i_2_n_4 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \TIMER[9]_i_1__2 
       (.I0(\TIMER_reg[10]_i_4_n_7 ),
        .I1(\STATE_reg_n_0_[3] ),
        .I2(\STATE_reg_n_0_[4] ),
        .O(\TIMER[9]_i_1__2_n_0 ));
  FDRE \TIMER_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\TIMER[0]_i_1_n_0 ),
        .Q(\TIMER_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \TIMER_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[10]_i_2_n_0 ),
        .Q(\TIMER_reg_n_0_[10] ),
        .R(\TIMER[10]_i_1_n_0 ));
  CARRY4 \TIMER_reg[10]_i_4 
       (.CI(\TIMER_reg[5]_i_2_n_0 ),
        .CO(\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\TIMER_reg_n_0_[10] ,\TIMER_reg_n_0_[9] }),
        .O({\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED [3],\TIMER_reg[10]_i_4_n_5 ,\TIMER_reg[10]_i_4_n_6 ,\TIMER_reg[10]_i_4_n_7 }),
        .S({1'b0,\TIMER[10]_i_5_n_0 ,\TIMER[10]_i_6_n_0 ,\TIMER[10]_i_7_n_0 }));
  FDSE \TIMER_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[11]_i_1_n_0 ),
        .Q(\TIMER_reg_n_0_[11] ),
        .S(\TIMER[10]_i_1_n_0 ));
  FDRE \TIMER_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[1]_i_1__2_n_0 ),
        .Q(\TIMER_reg_n_0_[1] ),
        .R(\TIMER[10]_i_1_n_0 ));
  FDSE \TIMER_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[2]_i_1_n_0 ),
        .Q(\TIMER_reg_n_0_[2] ),
        .S(\TIMER[10]_i_1_n_0 ));
  FDRE \TIMER_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[3]_i_1__2_n_0 ),
        .Q(\TIMER_reg_n_0_[3] ),
        .R(\TIMER[10]_i_1_n_0 ));
  FDRE \TIMER_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[4]_i_1__2_n_0 ),
        .Q(\TIMER_reg_n_0_[4] ),
        .R(\TIMER[10]_i_1_n_0 ));
  CARRY4 \TIMER_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\TIMER_reg[4]_i_2_n_0 ,\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(\TIMER_reg_n_0_[0] ),
        .DI({\TIMER_reg_n_0_[4] ,\TIMER_reg_n_0_[3] ,\TIMER_reg_n_0_[2] ,\TIMER_reg_n_0_[1] }),
        .O({\TIMER_reg[4]_i_2_n_4 ,\TIMER_reg[4]_i_2_n_5 ,\TIMER_reg[4]_i_2_n_6 ,\TIMER_reg[4]_i_2_n_7 }),
        .S({\TIMER[4]_i_3_n_0 ,\TIMER[4]_i_4_n_0 ,\TIMER[4]_i_5_n_0 ,\TIMER[4]_i_6_n_0 }));
  FDRE \TIMER_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[5]_i_1__2_n_0 ),
        .Q(\TIMER_reg_n_0_[5] ),
        .R(\TIMER[10]_i_1_n_0 ));
  CARRY4 \TIMER_reg[5]_i_2 
       (.CI(\TIMER_reg[4]_i_2_n_0 ),
        .CO({\TIMER_reg[5]_i_2_n_0 ,\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\TIMER_reg_n_0_[8] ,\TIMER_reg_n_0_[7] ,\TIMER_reg_n_0_[6] ,\TIMER_reg_n_0_[5] }),
        .O({\TIMER_reg[5]_i_2_n_4 ,\TIMER_reg[5]_i_2_n_5 ,\TIMER_reg[5]_i_2_n_6 ,\TIMER_reg[5]_i_2_n_7 }),
        .S({\TIMER[5]_i_3_n_0 ,\TIMER[5]_i_4_n_0 ,\TIMER[5]_i_5_n_0 ,\TIMER[5]_i_6_n_0 }));
  FDSE \TIMER_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[6]_i_1_n_0 ),
        .Q(\TIMER_reg_n_0_[6] ),
        .S(\TIMER[10]_i_1_n_0 ));
  FDSE \TIMER_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[7]_i_1_n_0 ),
        .Q(\TIMER_reg_n_0_[7] ),
        .S(\TIMER[10]_i_1_n_0 ));
  FDSE \TIMER_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[8]_i_1_n_0 ),
        .Q(\TIMER_reg_n_0_[8] ),
        .S(\TIMER[10]_i_1_n_0 ));
  FDRE \TIMER_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(g0_b0_n_0),
        .D(\TIMER[9]_i_1__2_n_0 ),
        .Q(\TIMER_reg_n_0_[9] ),
        .R(\TIMER[10]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h1DD5A001)) 
    g0_b0
       (.I0(\STATE_reg_n_0_[0] ),
        .I1(\STATE_reg_n_0_[1] ),
        .I2(\STATE_reg_n_0_[2] ),
        .I3(\STATE_reg_n_0_[3] ),
        .I4(\STATE_reg_n_0_[4] ),
        .O(g0_b0_n_0));
endmodule

module IOBUF_UNIQ_BASE_
   (IO,
    O,
    I,
    T);
  inout IO;
  output O;
  input I;
  input T;

  wire I;
  wire IO;
  wire O;
  wire T;

  IBUF IBUF
       (.I(IO),
        .O(O));
  OBUFT OBUFT
       (.I(I),
        .O(IO),
        .T(T));
endmodule

(* ORIG_REF_NAME = "IOBUF" *) 
module IOBUF_HD3
   (IO,
    O,
    I,
    T);
  inout IO;
  output O;
  input I;
  input T;

  wire I;
  wire IO;
  wire O;
  wire T;

  IBUF #(
    .IOSTANDARD("DEFAULT")) 
    IBUF
       (.I(IO),
        .O(O));
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    OBUFT
       (.I(I),
        .O(IO),
        .T(T));
endmodule

module PWM
   (LED_R_PWM_OBUF,
    ETH_CLK_OBUF);
  output LED_R_PWM_OBUF;
  input ETH_CLK_OBUF;

  wire \COUNT[0]_i_1__1_n_0 ;
  wire \COUNT[1]_i_1__1_n_0 ;
  wire \COUNT[1]_i_2_n_0 ;
  wire \COUNT[2]_i_1__0_n_0 ;
  wire \COUNT[3]_i_1_n_0 ;
  wire \COUNT[3]_i_2_n_0 ;
  wire \COUNT[4]_i_1_n_0 ;
  wire \COUNT[5]_i_1_n_0 ;
  wire \COUNT[6]_i_1_n_0 ;
  wire \COUNT[7]_i_1_n_0 ;
  wire \COUNT[7]_i_2_n_0 ;
  wire \COUNT[7]_i_3_n_0 ;
  wire \COUNT_reg_n_0_[0] ;
  wire \COUNT_reg_n_0_[1] ;
  wire \COUNT_reg_n_0_[2] ;
  wire \COUNT_reg_n_0_[3] ;
  wire \COUNT_reg_n_0_[4] ;
  wire \COUNT_reg_n_0_[5] ;
  wire \COUNT_reg_n_0_[6] ;
  wire \COUNT_reg_n_0_[7] ;
  wire ETH_CLK_OBUF;
  wire LED_R_PWM_OBUF;
  wire OUT_BIT_i_10_n_0;
  wire OUT_BIT_i_1_n_0;
  wire OUT_BIT_i_3_n_0;
  wire OUT_BIT_i_4_n_0;
  wire OUT_BIT_i_5_n_0;
  wire OUT_BIT_i_6_n_0;
  wire OUT_BIT_i_7_n_0;
  wire OUT_BIT_i_8_n_0;
  wire OUT_BIT_i_9_n_0;
  wire [9:0]TIMER;
  wire \TIMER[4]_i_2_n_0 ;
  wire \TIMER[9]_i_2_n_0 ;
  wire \TIMER_reg_n_0_[0] ;
  wire \TIMER_reg_n_0_[1] ;
  wire \TIMER_reg_n_0_[2] ;
  wire \TIMER_reg_n_0_[3] ;
  wire \TIMER_reg_n_0_[4] ;
  wire \TIMER_reg_n_0_[5] ;
  wire \TIMER_reg_n_0_[6] ;
  wire \TIMER_reg_n_0_[7] ;
  wire \TIMER_reg_n_0_[8] ;
  wire \TIMER_reg_n_0_[9] ;
  wire p_0_in;
  wire [2:0]NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED;
  wire [3:0]NLW_OUT_BIT_reg_i_2_O_UNCONNECTED;

  LUT6 #(
    .INIT(64'h2333333333333333)) 
    \COUNT[0]_i_1__1 
       (.I0(\COUNT[7]_i_3_n_0 ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[5] ),
        .I3(\COUNT_reg_n_0_[4] ),
        .I4(\COUNT_reg_n_0_[7] ),
        .I5(\COUNT_reg_n_0_[6] ),
        .O(\COUNT[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00FFBF00)) 
    \COUNT[1]_i_1__1 
       (.I0(\COUNT[1]_i_2_n_0 ),
        .I1(\COUNT_reg_n_0_[3] ),
        .I2(\COUNT_reg_n_0_[2] ),
        .I3(\COUNT_reg_n_0_[1] ),
        .I4(\COUNT_reg_n_0_[0] ),
        .O(\COUNT[1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \COUNT[1]_i_2 
       (.I0(\COUNT_reg_n_0_[5] ),
        .I1(\COUNT_reg_n_0_[4] ),
        .I2(\COUNT_reg_n_0_[7] ),
        .I3(\COUNT_reg_n_0_[6] ),
        .O(\COUNT[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'hFFC011C0)) 
    \COUNT[2]_i_1__0 
       (.I0(\COUNT_reg_n_0_[3] ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[1] ),
        .I3(\COUNT_reg_n_0_[2] ),
        .I4(\COUNT[3]_i_2_n_0 ),
        .O(\COUNT[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'hFF805580)) 
    \COUNT[3]_i_1 
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .I2(\COUNT_reg_n_0_[0] ),
        .I3(\COUNT_reg_n_0_[3] ),
        .I4(\COUNT[3]_i_2_n_0 ),
        .O(\COUNT[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h15555555FFFFFFFF)) 
    \COUNT[3]_i_2 
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .I2(\COUNT_reg_n_0_[4] ),
        .I3(\COUNT_reg_n_0_[7] ),
        .I4(\COUNT_reg_n_0_[6] ),
        .I5(\COUNT_reg_n_0_[1] ),
        .O(\COUNT[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF00FF7F00FF0000)) 
    \COUNT[4]_i_1 
       (.I0(\COUNT_reg_n_0_[7] ),
        .I1(\COUNT_reg_n_0_[6] ),
        .I2(\COUNT_reg_n_0_[5] ),
        .I3(\COUNT[7]_i_3_n_0 ),
        .I4(\COUNT_reg_n_0_[0] ),
        .I5(\COUNT_reg_n_0_[4] ),
        .O(\COUNT[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFFF55000000)) 
    \COUNT[5]_i_1 
       (.I0(\COUNT[7]_i_3_n_0 ),
        .I1(\COUNT_reg_n_0_[7] ),
        .I2(\COUNT_reg_n_0_[6] ),
        .I3(\COUNT_reg_n_0_[0] ),
        .I4(\COUNT_reg_n_0_[4] ),
        .I5(\COUNT_reg_n_0_[5] ),
        .O(\COUNT[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF01CF0F0F0F0F0F0)) 
    \COUNT[6]_i_1 
       (.I0(\COUNT_reg_n_0_[7] ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[6] ),
        .I3(\COUNT[7]_i_3_n_0 ),
        .I4(\COUNT_reg_n_0_[5] ),
        .I5(\COUNT_reg_n_0_[4] ),
        .O(\COUNT[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \COUNT[7]_i_1 
       (.I0(\TIMER_reg_n_0_[9] ),
        .I1(\TIMER_reg_n_0_[7] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[6] ),
        .I4(\TIMER_reg_n_0_[8] ),
        .I5(\TIMER[9]_i_2_n_0 ),
        .O(\COUNT[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFF7FF08000000)) 
    \COUNT[7]_i_2 
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .I2(\COUNT[7]_i_3_n_0 ),
        .I3(\COUNT_reg_n_0_[6] ),
        .I4(\COUNT_reg_n_0_[0] ),
        .I5(\COUNT_reg_n_0_[7] ),
        .O(\COUNT[7]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \COUNT[7]_i_3 
       (.I0(\COUNT_reg_n_0_[3] ),
        .I1(\COUNT_reg_n_0_[2] ),
        .I2(\COUNT_reg_n_0_[1] ),
        .O(\COUNT[7]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1_n_0 ),
        .D(\COUNT[0]_i_1__1_n_0 ),
        .Q(\COUNT_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1_n_0 ),
        .D(\COUNT[1]_i_1__1_n_0 ),
        .Q(\COUNT_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1_n_0 ),
        .D(\COUNT[2]_i_1__0_n_0 ),
        .Q(\COUNT_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1_n_0 ),
        .D(\COUNT[3]_i_1_n_0 ),
        .Q(\COUNT_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1_n_0 ),
        .D(\COUNT[4]_i_1_n_0 ),
        .Q(\COUNT_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1_n_0 ),
        .D(\COUNT[5]_i_1_n_0 ),
        .Q(\COUNT_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1_n_0 ),
        .D(\COUNT[6]_i_1_n_0 ),
        .Q(\COUNT_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1_n_0 ),
        .D(\COUNT[7]_i_2_n_0 ),
        .Q(\COUNT_reg_n_0_[7] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    OUT_BIT_i_1
       (.I0(p_0_in),
        .O(OUT_BIT_i_1_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_10
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .O(OUT_BIT_i_10_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_3
       (.I0(\COUNT_reg_n_0_[6] ),
        .I1(\COUNT_reg_n_0_[7] ),
        .O(OUT_BIT_i_3_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_4
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .O(OUT_BIT_i_4_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_5
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[3] ),
        .O(OUT_BIT_i_5_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_6
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .O(OUT_BIT_i_6_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_7
       (.I0(\COUNT_reg_n_0_[6] ),
        .I1(\COUNT_reg_n_0_[7] ),
        .O(OUT_BIT_i_7_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_8
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .O(OUT_BIT_i_8_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_9
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[3] ),
        .O(OUT_BIT_i_9_n_0));
  FDRE OUT_BIT_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(OUT_BIT_i_1_n_0),
        .Q(LED_R_PWM_OBUF),
        .R(1'b0));
  CARRY4 OUT_BIT_reg_i_2
       (.CI(1'b0),
        .CO({p_0_in,NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({OUT_BIT_i_3_n_0,OUT_BIT_i_4_n_0,OUT_BIT_i_5_n_0,OUT_BIT_i_6_n_0}),
        .O(NLW_OUT_BIT_reg_i_2_O_UNCONNECTED[3:0]),
        .S({OUT_BIT_i_7_n_0,OUT_BIT_i_8_n_0,OUT_BIT_i_9_n_0,OUT_BIT_i_10_n_0}));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[0]_i_1__0 
       (.I0(\TIMER_reg_n_0_[0] ),
        .O(TIMER[0]));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \TIMER[1]_i_1 
       (.I0(\TIMER_reg_n_0_[1] ),
        .I1(\TIMER_reg_n_0_[0] ),
        .O(TIMER[1]));
  LUT3 #(
    .INIT(8'hA9)) 
    \TIMER[2]_i_1__0 
       (.I0(\TIMER_reg_n_0_[2] ),
        .I1(\TIMER_reg_n_0_[0] ),
        .I2(\TIMER_reg_n_0_[1] ),
        .O(TIMER[2]));
  LUT6 #(
    .INIT(64'hF0F0F0F0F0F0F00E)) 
    \TIMER[3]_i_1 
       (.I0(\TIMER[4]_i_2_n_0 ),
        .I1(\TIMER_reg_n_0_[4] ),
        .I2(\TIMER_reg_n_0_[3] ),
        .I3(\TIMER_reg_n_0_[1] ),
        .I4(\TIMER_reg_n_0_[0] ),
        .I5(\TIMER_reg_n_0_[2] ),
        .O(TIMER[3]));
  LUT6 #(
    .INIT(64'hFFFE0001FFFE0000)) 
    \TIMER[4]_i_1 
       (.I0(\TIMER_reg_n_0_[3] ),
        .I1(\TIMER_reg_n_0_[1] ),
        .I2(\TIMER_reg_n_0_[0] ),
        .I3(\TIMER_reg_n_0_[2] ),
        .I4(\TIMER_reg_n_0_[4] ),
        .I5(\TIMER[4]_i_2_n_0 ),
        .O(TIMER[4]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \TIMER[4]_i_2 
       (.I0(\TIMER_reg_n_0_[8] ),
        .I1(\TIMER_reg_n_0_[6] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[7] ),
        .I4(\TIMER_reg_n_0_[9] ),
        .O(\TIMER[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \TIMER[5]_i_1 
       (.I0(\TIMER_reg_n_0_[5] ),
        .I1(\TIMER_reg_n_0_[3] ),
        .I2(\TIMER_reg_n_0_[1] ),
        .I3(\TIMER_reg_n_0_[0] ),
        .I4(\TIMER_reg_n_0_[2] ),
        .I5(\TIMER_reg_n_0_[4] ),
        .O(TIMER[5]));
  LUT3 #(
    .INIT(8'hE1)) 
    \TIMER[6]_i_1__0 
       (.I0(\TIMER[9]_i_2_n_0 ),
        .I1(\TIMER_reg_n_0_[5] ),
        .I2(\TIMER_reg_n_0_[6] ),
        .O(TIMER[6]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \TIMER[7]_i_1__0 
       (.I0(\TIMER[9]_i_2_n_0 ),
        .I1(\TIMER_reg_n_0_[6] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[7] ),
        .O(TIMER[7]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \TIMER[8]_i_1__0 
       (.I0(\TIMER[9]_i_2_n_0 ),
        .I1(\TIMER_reg_n_0_[7] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[6] ),
        .I4(\TIMER_reg_n_0_[8] ),
        .O(TIMER[8]));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \TIMER[9]_i_1 
       (.I0(\TIMER[9]_i_2_n_0 ),
        .I1(\TIMER_reg_n_0_[8] ),
        .I2(\TIMER_reg_n_0_[6] ),
        .I3(\TIMER_reg_n_0_[5] ),
        .I4(\TIMER_reg_n_0_[7] ),
        .I5(\TIMER_reg_n_0_[9] ),
        .O(TIMER[9]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \TIMER[9]_i_2 
       (.I0(\TIMER_reg_n_0_[3] ),
        .I1(\TIMER_reg_n_0_[1] ),
        .I2(\TIMER_reg_n_0_[0] ),
        .I3(\TIMER_reg_n_0_[2] ),
        .I4(\TIMER_reg_n_0_[4] ),
        .O(\TIMER[9]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[0]),
        .Q(\TIMER_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[1]),
        .Q(\TIMER_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[2]),
        .Q(\TIMER_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TIMER_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[3]),
        .Q(\TIMER_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TIMER_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[4]),
        .Q(\TIMER_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[5]),
        .Q(\TIMER_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[6]),
        .Q(\TIMER_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[7]),
        .Q(\TIMER_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[8]),
        .Q(\TIMER_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[9]),
        .Q(\TIMER_reg_n_0_[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "PWM" *) 
module PWM_0
   (LED_G_PWM_OBUF,
    ETH_CLK_OBUF);
  output LED_G_PWM_OBUF;
  input ETH_CLK_OBUF;

  wire \COUNT[0]_i_1__2_n_0 ;
  wire \COUNT[1]_i_1__2_n_0 ;
  wire \COUNT[1]_i_2__0_n_0 ;
  wire \COUNT[2]_i_1__1_n_0 ;
  wire \COUNT[3]_i_1__0_n_0 ;
  wire \COUNT[3]_i_2__0_n_0 ;
  wire \COUNT[4]_i_1__0_n_0 ;
  wire \COUNT[5]_i_1__0_n_0 ;
  wire \COUNT[6]_i_1__0_n_0 ;
  wire \COUNT[7]_i_1__0_n_0 ;
  wire \COUNT[7]_i_2__0_n_0 ;
  wire \COUNT[7]_i_3__0_n_0 ;
  wire \COUNT_reg_n_0_[0] ;
  wire \COUNT_reg_n_0_[1] ;
  wire \COUNT_reg_n_0_[2] ;
  wire \COUNT_reg_n_0_[3] ;
  wire \COUNT_reg_n_0_[4] ;
  wire \COUNT_reg_n_0_[5] ;
  wire \COUNT_reg_n_0_[6] ;
  wire \COUNT_reg_n_0_[7] ;
  wire ETH_CLK_OBUF;
  wire LED_G_PWM_OBUF;
  wire OUT_BIT_i_10__0_n_0;
  wire OUT_BIT_i_1__0_n_0;
  wire OUT_BIT_i_3__0_n_0;
  wire OUT_BIT_i_4__0_n_0;
  wire OUT_BIT_i_5__0_n_0;
  wire OUT_BIT_i_6__0_n_0;
  wire OUT_BIT_i_7__0_n_0;
  wire OUT_BIT_i_8__0_n_0;
  wire OUT_BIT_i_9__0_n_0;
  wire [9:0]TIMER;
  wire \TIMER[4]_i_2__0_n_0 ;
  wire \TIMER[9]_i_2__0_n_0 ;
  wire \TIMER_reg_n_0_[0] ;
  wire \TIMER_reg_n_0_[1] ;
  wire \TIMER_reg_n_0_[2] ;
  wire \TIMER_reg_n_0_[3] ;
  wire \TIMER_reg_n_0_[4] ;
  wire \TIMER_reg_n_0_[5] ;
  wire \TIMER_reg_n_0_[6] ;
  wire \TIMER_reg_n_0_[7] ;
  wire \TIMER_reg_n_0_[8] ;
  wire \TIMER_reg_n_0_[9] ;
  wire p_0_in;
  wire [2:0]NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED;
  wire [3:0]NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED;

  LUT6 #(
    .INIT(64'h2333333333333333)) 
    \COUNT[0]_i_1__2 
       (.I0(\COUNT[7]_i_3__0_n_0 ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[5] ),
        .I3(\COUNT_reg_n_0_[4] ),
        .I4(\COUNT_reg_n_0_[7] ),
        .I5(\COUNT_reg_n_0_[6] ),
        .O(\COUNT[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00FFBF00)) 
    \COUNT[1]_i_1__2 
       (.I0(\COUNT[1]_i_2__0_n_0 ),
        .I1(\COUNT_reg_n_0_[3] ),
        .I2(\COUNT_reg_n_0_[2] ),
        .I3(\COUNT_reg_n_0_[1] ),
        .I4(\COUNT_reg_n_0_[0] ),
        .O(\COUNT[1]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \COUNT[1]_i_2__0 
       (.I0(\COUNT_reg_n_0_[5] ),
        .I1(\COUNT_reg_n_0_[4] ),
        .I2(\COUNT_reg_n_0_[7] ),
        .I3(\COUNT_reg_n_0_[6] ),
        .O(\COUNT[1]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT5 #(
    .INIT(32'hFFC011C0)) 
    \COUNT[2]_i_1__1 
       (.I0(\COUNT_reg_n_0_[3] ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[1] ),
        .I3(\COUNT_reg_n_0_[2] ),
        .I4(\COUNT[3]_i_2__0_n_0 ),
        .O(\COUNT[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT5 #(
    .INIT(32'hFF805580)) 
    \COUNT[3]_i_1__0 
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .I2(\COUNT_reg_n_0_[0] ),
        .I3(\COUNT_reg_n_0_[3] ),
        .I4(\COUNT[3]_i_2__0_n_0 ),
        .O(\COUNT[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h15555555FFFFFFFF)) 
    \COUNT[3]_i_2__0 
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .I2(\COUNT_reg_n_0_[4] ),
        .I3(\COUNT_reg_n_0_[7] ),
        .I4(\COUNT_reg_n_0_[6] ),
        .I5(\COUNT_reg_n_0_[1] ),
        .O(\COUNT[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF00FF7F00FF0000)) 
    \COUNT[4]_i_1__0 
       (.I0(\COUNT_reg_n_0_[7] ),
        .I1(\COUNT_reg_n_0_[6] ),
        .I2(\COUNT_reg_n_0_[5] ),
        .I3(\COUNT[7]_i_3__0_n_0 ),
        .I4(\COUNT_reg_n_0_[0] ),
        .I5(\COUNT_reg_n_0_[4] ),
        .O(\COUNT[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFFF55000000)) 
    \COUNT[5]_i_1__0 
       (.I0(\COUNT[7]_i_3__0_n_0 ),
        .I1(\COUNT_reg_n_0_[7] ),
        .I2(\COUNT_reg_n_0_[6] ),
        .I3(\COUNT_reg_n_0_[0] ),
        .I4(\COUNT_reg_n_0_[4] ),
        .I5(\COUNT_reg_n_0_[5] ),
        .O(\COUNT[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF01CF0F0F0F0F0F0)) 
    \COUNT[6]_i_1__0 
       (.I0(\COUNT_reg_n_0_[7] ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[6] ),
        .I3(\COUNT[7]_i_3__0_n_0 ),
        .I4(\COUNT_reg_n_0_[5] ),
        .I5(\COUNT_reg_n_0_[4] ),
        .O(\COUNT[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \COUNT[7]_i_1__0 
       (.I0(\TIMER_reg_n_0_[9] ),
        .I1(\TIMER_reg_n_0_[7] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[6] ),
        .I4(\TIMER_reg_n_0_[8] ),
        .I5(\TIMER[9]_i_2__0_n_0 ),
        .O(\COUNT[7]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFF7FF08000000)) 
    \COUNT[7]_i_2__0 
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .I2(\COUNT[7]_i_3__0_n_0 ),
        .I3(\COUNT_reg_n_0_[6] ),
        .I4(\COUNT_reg_n_0_[0] ),
        .I5(\COUNT_reg_n_0_[7] ),
        .O(\COUNT[7]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \COUNT[7]_i_3__0 
       (.I0(\COUNT_reg_n_0_[3] ),
        .I1(\COUNT_reg_n_0_[2] ),
        .I2(\COUNT_reg_n_0_[1] ),
        .O(\COUNT[7]_i_3__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__0_n_0 ),
        .D(\COUNT[0]_i_1__2_n_0 ),
        .Q(\COUNT_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__0_n_0 ),
        .D(\COUNT[1]_i_1__2_n_0 ),
        .Q(\COUNT_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__0_n_0 ),
        .D(\COUNT[2]_i_1__1_n_0 ),
        .Q(\COUNT_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__0_n_0 ),
        .D(\COUNT[3]_i_1__0_n_0 ),
        .Q(\COUNT_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__0_n_0 ),
        .D(\COUNT[4]_i_1__0_n_0 ),
        .Q(\COUNT_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__0_n_0 ),
        .D(\COUNT[5]_i_1__0_n_0 ),
        .Q(\COUNT_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__0_n_0 ),
        .D(\COUNT[6]_i_1__0_n_0 ),
        .Q(\COUNT_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__0_n_0 ),
        .D(\COUNT[7]_i_2__0_n_0 ),
        .Q(\COUNT_reg_n_0_[7] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_10__0
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .O(OUT_BIT_i_10__0_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    OUT_BIT_i_1__0
       (.I0(p_0_in),
        .O(OUT_BIT_i_1__0_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_3__0
       (.I0(\COUNT_reg_n_0_[6] ),
        .I1(\COUNT_reg_n_0_[7] ),
        .O(OUT_BIT_i_3__0_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_4__0
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .O(OUT_BIT_i_4__0_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_5__0
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[3] ),
        .O(OUT_BIT_i_5__0_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_6__0
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .O(OUT_BIT_i_6__0_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_7__0
       (.I0(\COUNT_reg_n_0_[6] ),
        .I1(\COUNT_reg_n_0_[7] ),
        .O(OUT_BIT_i_7__0_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_8__0
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .O(OUT_BIT_i_8__0_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_9__0
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[3] ),
        .O(OUT_BIT_i_9__0_n_0));
  FDRE OUT_BIT_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(OUT_BIT_i_1__0_n_0),
        .Q(LED_G_PWM_OBUF),
        .R(1'b0));
  CARRY4 OUT_BIT_reg_i_2__0
       (.CI(1'b0),
        .CO({p_0_in,NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({OUT_BIT_i_3__0_n_0,OUT_BIT_i_4__0_n_0,OUT_BIT_i_5__0_n_0,OUT_BIT_i_6__0_n_0}),
        .O(NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED[3:0]),
        .S({OUT_BIT_i_7__0_n_0,OUT_BIT_i_8__0_n_0,OUT_BIT_i_9__0_n_0,OUT_BIT_i_10__0_n_0}));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[0]_i_1__1 
       (.I0(\TIMER_reg_n_0_[0] ),
        .O(TIMER[0]));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \TIMER[1]_i_1__0 
       (.I0(\TIMER_reg_n_0_[1] ),
        .I1(\TIMER_reg_n_0_[0] ),
        .O(TIMER[1]));
  LUT3 #(
    .INIT(8'hA9)) 
    \TIMER[2]_i_1__1 
       (.I0(\TIMER_reg_n_0_[2] ),
        .I1(\TIMER_reg_n_0_[0] ),
        .I2(\TIMER_reg_n_0_[1] ),
        .O(TIMER[2]));
  LUT6 #(
    .INIT(64'hF0F0F0F0F0F0F00E)) 
    \TIMER[3]_i_1__0 
       (.I0(\TIMER[4]_i_2__0_n_0 ),
        .I1(\TIMER_reg_n_0_[4] ),
        .I2(\TIMER_reg_n_0_[3] ),
        .I3(\TIMER_reg_n_0_[1] ),
        .I4(\TIMER_reg_n_0_[0] ),
        .I5(\TIMER_reg_n_0_[2] ),
        .O(TIMER[3]));
  LUT6 #(
    .INIT(64'hFFFE0001FFFE0000)) 
    \TIMER[4]_i_1__0 
       (.I0(\TIMER_reg_n_0_[3] ),
        .I1(\TIMER_reg_n_0_[1] ),
        .I2(\TIMER_reg_n_0_[0] ),
        .I3(\TIMER_reg_n_0_[2] ),
        .I4(\TIMER_reg_n_0_[4] ),
        .I5(\TIMER[4]_i_2__0_n_0 ),
        .O(TIMER[4]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \TIMER[4]_i_2__0 
       (.I0(\TIMER_reg_n_0_[8] ),
        .I1(\TIMER_reg_n_0_[6] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[7] ),
        .I4(\TIMER_reg_n_0_[9] ),
        .O(\TIMER[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \TIMER[5]_i_1__0 
       (.I0(\TIMER_reg_n_0_[5] ),
        .I1(\TIMER_reg_n_0_[3] ),
        .I2(\TIMER_reg_n_0_[1] ),
        .I3(\TIMER_reg_n_0_[0] ),
        .I4(\TIMER_reg_n_0_[2] ),
        .I5(\TIMER_reg_n_0_[4] ),
        .O(TIMER[5]));
  LUT3 #(
    .INIT(8'hE1)) 
    \TIMER[6]_i_1__1 
       (.I0(\TIMER[9]_i_2__0_n_0 ),
        .I1(\TIMER_reg_n_0_[5] ),
        .I2(\TIMER_reg_n_0_[6] ),
        .O(TIMER[6]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \TIMER[7]_i_1__1 
       (.I0(\TIMER[9]_i_2__0_n_0 ),
        .I1(\TIMER_reg_n_0_[6] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[7] ),
        .O(TIMER[7]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \TIMER[8]_i_1__1 
       (.I0(\TIMER[9]_i_2__0_n_0 ),
        .I1(\TIMER_reg_n_0_[7] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[6] ),
        .I4(\TIMER_reg_n_0_[8] ),
        .O(TIMER[8]));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \TIMER[9]_i_1__0 
       (.I0(\TIMER[9]_i_2__0_n_0 ),
        .I1(\TIMER_reg_n_0_[8] ),
        .I2(\TIMER_reg_n_0_[6] ),
        .I3(\TIMER_reg_n_0_[5] ),
        .I4(\TIMER_reg_n_0_[7] ),
        .I5(\TIMER_reg_n_0_[9] ),
        .O(TIMER[9]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \TIMER[9]_i_2__0 
       (.I0(\TIMER_reg_n_0_[3] ),
        .I1(\TIMER_reg_n_0_[1] ),
        .I2(\TIMER_reg_n_0_[0] ),
        .I3(\TIMER_reg_n_0_[2] ),
        .I4(\TIMER_reg_n_0_[4] ),
        .O(\TIMER[9]_i_2__0_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[0]),
        .Q(\TIMER_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[1]),
        .Q(\TIMER_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[2]),
        .Q(\TIMER_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TIMER_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[3]),
        .Q(\TIMER_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TIMER_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[4]),
        .Q(\TIMER_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[5]),
        .Q(\TIMER_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[6]),
        .Q(\TIMER_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[7]),
        .Q(\TIMER_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[8]),
        .Q(\TIMER_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[9]),
        .Q(\TIMER_reg_n_0_[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "PWM" *) 
module PWM_1
   (LED_B_PWM_OBUF,
    ETH_CLK_OBUF);
  output LED_B_PWM_OBUF;
  input ETH_CLK_OBUF;

  wire \COUNT[0]_i_1__3_n_0 ;
  wire \COUNT[1]_i_1__3_n_0 ;
  wire \COUNT[1]_i_2__1_n_0 ;
  wire \COUNT[2]_i_1__2_n_0 ;
  wire \COUNT[3]_i_1__1_n_0 ;
  wire \COUNT[3]_i_2__1_n_0 ;
  wire \COUNT[4]_i_1__1_n_0 ;
  wire \COUNT[5]_i_1__1_n_0 ;
  wire \COUNT[6]_i_1__1_n_0 ;
  wire \COUNT[7]_i_1__1_n_0 ;
  wire \COUNT[7]_i_2__1_n_0 ;
  wire \COUNT[7]_i_3__1_n_0 ;
  wire \COUNT_reg_n_0_[0] ;
  wire \COUNT_reg_n_0_[1] ;
  wire \COUNT_reg_n_0_[2] ;
  wire \COUNT_reg_n_0_[3] ;
  wire \COUNT_reg_n_0_[4] ;
  wire \COUNT_reg_n_0_[5] ;
  wire \COUNT_reg_n_0_[6] ;
  wire \COUNT_reg_n_0_[7] ;
  wire ETH_CLK_OBUF;
  wire LED_B_PWM_OBUF;
  wire OUT_BIT_i_10__1_n_0;
  wire OUT_BIT_i_1__1_n_0;
  wire OUT_BIT_i_3__1_n_0;
  wire OUT_BIT_i_4__1_n_0;
  wire OUT_BIT_i_5__1_n_0;
  wire OUT_BIT_i_6__1_n_0;
  wire OUT_BIT_i_7__1_n_0;
  wire OUT_BIT_i_8__1_n_0;
  wire OUT_BIT_i_9__1_n_0;
  wire [9:0]TIMER;
  wire \TIMER[4]_i_2__1_n_0 ;
  wire \TIMER[9]_i_2__1_n_0 ;
  wire \TIMER_reg_n_0_[0] ;
  wire \TIMER_reg_n_0_[1] ;
  wire \TIMER_reg_n_0_[2] ;
  wire \TIMER_reg_n_0_[3] ;
  wire \TIMER_reg_n_0_[4] ;
  wire \TIMER_reg_n_0_[5] ;
  wire \TIMER_reg_n_0_[6] ;
  wire \TIMER_reg_n_0_[7] ;
  wire \TIMER_reg_n_0_[8] ;
  wire \TIMER_reg_n_0_[9] ;
  wire p_0_in;
  wire [2:0]NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED;
  wire [3:0]NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED;

  LUT6 #(
    .INIT(64'h2333333333333333)) 
    \COUNT[0]_i_1__3 
       (.I0(\COUNT[7]_i_3__1_n_0 ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[5] ),
        .I3(\COUNT_reg_n_0_[4] ),
        .I4(\COUNT_reg_n_0_[7] ),
        .I5(\COUNT_reg_n_0_[6] ),
        .O(\COUNT[0]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h00FFBF00)) 
    \COUNT[1]_i_1__3 
       (.I0(\COUNT[1]_i_2__1_n_0 ),
        .I1(\COUNT_reg_n_0_[3] ),
        .I2(\COUNT_reg_n_0_[2] ),
        .I3(\COUNT_reg_n_0_[1] ),
        .I4(\COUNT_reg_n_0_[0] ),
        .O(\COUNT[1]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \COUNT[1]_i_2__1 
       (.I0(\COUNT_reg_n_0_[5] ),
        .I1(\COUNT_reg_n_0_[4] ),
        .I2(\COUNT_reg_n_0_[7] ),
        .I3(\COUNT_reg_n_0_[6] ),
        .O(\COUNT[1]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT5 #(
    .INIT(32'hFFC011C0)) 
    \COUNT[2]_i_1__2 
       (.I0(\COUNT_reg_n_0_[3] ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[1] ),
        .I3(\COUNT_reg_n_0_[2] ),
        .I4(\COUNT[3]_i_2__1_n_0 ),
        .O(\COUNT[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT5 #(
    .INIT(32'hFF805580)) 
    \COUNT[3]_i_1__1 
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .I2(\COUNT_reg_n_0_[0] ),
        .I3(\COUNT_reg_n_0_[3] ),
        .I4(\COUNT[3]_i_2__1_n_0 ),
        .O(\COUNT[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h15555555FFFFFFFF)) 
    \COUNT[3]_i_2__1 
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .I2(\COUNT_reg_n_0_[4] ),
        .I3(\COUNT_reg_n_0_[7] ),
        .I4(\COUNT_reg_n_0_[6] ),
        .I5(\COUNT_reg_n_0_[1] ),
        .O(\COUNT[3]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFF00FF7F00FF0000)) 
    \COUNT[4]_i_1__1 
       (.I0(\COUNT_reg_n_0_[7] ),
        .I1(\COUNT_reg_n_0_[6] ),
        .I2(\COUNT_reg_n_0_[5] ),
        .I3(\COUNT[7]_i_3__1_n_0 ),
        .I4(\COUNT_reg_n_0_[0] ),
        .I5(\COUNT_reg_n_0_[4] ),
        .O(\COUNT[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFFF55000000)) 
    \COUNT[5]_i_1__1 
       (.I0(\COUNT[7]_i_3__1_n_0 ),
        .I1(\COUNT_reg_n_0_[7] ),
        .I2(\COUNT_reg_n_0_[6] ),
        .I3(\COUNT_reg_n_0_[0] ),
        .I4(\COUNT_reg_n_0_[4] ),
        .I5(\COUNT_reg_n_0_[5] ),
        .O(\COUNT[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF01CF0F0F0F0F0F0)) 
    \COUNT[6]_i_1__1 
       (.I0(\COUNT_reg_n_0_[7] ),
        .I1(\COUNT_reg_n_0_[0] ),
        .I2(\COUNT_reg_n_0_[6] ),
        .I3(\COUNT[7]_i_3__1_n_0 ),
        .I4(\COUNT_reg_n_0_[5] ),
        .I5(\COUNT_reg_n_0_[4] ),
        .O(\COUNT[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \COUNT[7]_i_1__1 
       (.I0(\TIMER_reg_n_0_[9] ),
        .I1(\TIMER_reg_n_0_[7] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[6] ),
        .I4(\TIMER_reg_n_0_[8] ),
        .I5(\TIMER[9]_i_2__1_n_0 ),
        .O(\COUNT[7]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFF7FF08000000)) 
    \COUNT[7]_i_2__1 
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .I2(\COUNT[7]_i_3__1_n_0 ),
        .I3(\COUNT_reg_n_0_[6] ),
        .I4(\COUNT_reg_n_0_[0] ),
        .I5(\COUNT_reg_n_0_[7] ),
        .O(\COUNT[7]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \COUNT[7]_i_3__1 
       (.I0(\COUNT_reg_n_0_[3] ),
        .I1(\COUNT_reg_n_0_[2] ),
        .I2(\COUNT_reg_n_0_[1] ),
        .O(\COUNT[7]_i_3__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__1_n_0 ),
        .D(\COUNT[0]_i_1__3_n_0 ),
        .Q(\COUNT_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__1_n_0 ),
        .D(\COUNT[1]_i_1__3_n_0 ),
        .Q(\COUNT_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__1_n_0 ),
        .D(\COUNT[2]_i_1__2_n_0 ),
        .Q(\COUNT_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__1_n_0 ),
        .D(\COUNT[3]_i_1__1_n_0 ),
        .Q(\COUNT_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__1_n_0 ),
        .D(\COUNT[4]_i_1__1_n_0 ),
        .Q(\COUNT_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__1_n_0 ),
        .D(\COUNT[5]_i_1__1_n_0 ),
        .Q(\COUNT_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__1_n_0 ),
        .D(\COUNT[6]_i_1__1_n_0 ),
        .Q(\COUNT_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \COUNT_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[7]_i_1__1_n_0 ),
        .D(\COUNT[7]_i_2__1_n_0 ),
        .Q(\COUNT_reg_n_0_[7] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_10__1
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .O(OUT_BIT_i_10__1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    OUT_BIT_i_1__1
       (.I0(p_0_in),
        .O(OUT_BIT_i_1__1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_3__1
       (.I0(\COUNT_reg_n_0_[6] ),
        .I1(\COUNT_reg_n_0_[7] ),
        .O(OUT_BIT_i_3__1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_4__1
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .O(OUT_BIT_i_4__1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_5__1
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[3] ),
        .O(OUT_BIT_i_5__1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    OUT_BIT_i_6__1
       (.I0(\COUNT_reg_n_0_[0] ),
        .I1(\COUNT_reg_n_0_[1] ),
        .O(OUT_BIT_i_6__1_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_7__1
       (.I0(\COUNT_reg_n_0_[6] ),
        .I1(\COUNT_reg_n_0_[7] ),
        .O(OUT_BIT_i_7__1_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_8__1
       (.I0(\COUNT_reg_n_0_[4] ),
        .I1(\COUNT_reg_n_0_[5] ),
        .O(OUT_BIT_i_8__1_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    OUT_BIT_i_9__1
       (.I0(\COUNT_reg_n_0_[2] ),
        .I1(\COUNT_reg_n_0_[3] ),
        .O(OUT_BIT_i_9__1_n_0));
  FDRE OUT_BIT_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(OUT_BIT_i_1__1_n_0),
        .Q(LED_B_PWM_OBUF),
        .R(1'b0));
  CARRY4 OUT_BIT_reg_i_2__1
       (.CI(1'b0),
        .CO({p_0_in,NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({OUT_BIT_i_3__1_n_0,OUT_BIT_i_4__1_n_0,OUT_BIT_i_5__1_n_0,OUT_BIT_i_6__1_n_0}),
        .O(NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED[3:0]),
        .S({OUT_BIT_i_7__1_n_0,OUT_BIT_i_8__1_n_0,OUT_BIT_i_9__1_n_0,OUT_BIT_i_10__1_n_0}));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \TIMER[0]_i_1__2 
       (.I0(\TIMER_reg_n_0_[0] ),
        .O(TIMER[0]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \TIMER[1]_i_1__1 
       (.I0(\TIMER_reg_n_0_[1] ),
        .I1(\TIMER_reg_n_0_[0] ),
        .O(TIMER[1]));
  LUT3 #(
    .INIT(8'hA9)) 
    \TIMER[2]_i_1__2 
       (.I0(\TIMER_reg_n_0_[2] ),
        .I1(\TIMER_reg_n_0_[0] ),
        .I2(\TIMER_reg_n_0_[1] ),
        .O(TIMER[2]));
  LUT6 #(
    .INIT(64'hF0F0F0F0F0F0F00E)) 
    \TIMER[3]_i_1__1 
       (.I0(\TIMER[4]_i_2__1_n_0 ),
        .I1(\TIMER_reg_n_0_[4] ),
        .I2(\TIMER_reg_n_0_[3] ),
        .I3(\TIMER_reg_n_0_[1] ),
        .I4(\TIMER_reg_n_0_[0] ),
        .I5(\TIMER_reg_n_0_[2] ),
        .O(TIMER[3]));
  LUT6 #(
    .INIT(64'hFFFE0001FFFE0000)) 
    \TIMER[4]_i_1__1 
       (.I0(\TIMER_reg_n_0_[3] ),
        .I1(\TIMER_reg_n_0_[1] ),
        .I2(\TIMER_reg_n_0_[0] ),
        .I3(\TIMER_reg_n_0_[2] ),
        .I4(\TIMER_reg_n_0_[4] ),
        .I5(\TIMER[4]_i_2__1_n_0 ),
        .O(TIMER[4]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \TIMER[4]_i_2__1 
       (.I0(\TIMER_reg_n_0_[8] ),
        .I1(\TIMER_reg_n_0_[6] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[7] ),
        .I4(\TIMER_reg_n_0_[9] ),
        .O(\TIMER[4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \TIMER[5]_i_1__1 
       (.I0(\TIMER_reg_n_0_[5] ),
        .I1(\TIMER_reg_n_0_[3] ),
        .I2(\TIMER_reg_n_0_[1] ),
        .I3(\TIMER_reg_n_0_[0] ),
        .I4(\TIMER_reg_n_0_[2] ),
        .I5(\TIMER_reg_n_0_[4] ),
        .O(TIMER[5]));
  LUT3 #(
    .INIT(8'hE1)) 
    \TIMER[6]_i_1__2 
       (.I0(\TIMER[9]_i_2__1_n_0 ),
        .I1(\TIMER_reg_n_0_[5] ),
        .I2(\TIMER_reg_n_0_[6] ),
        .O(TIMER[6]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \TIMER[7]_i_1__2 
       (.I0(\TIMER[9]_i_2__1_n_0 ),
        .I1(\TIMER_reg_n_0_[6] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[7] ),
        .O(TIMER[7]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \TIMER[8]_i_1__2 
       (.I0(\TIMER[9]_i_2__1_n_0 ),
        .I1(\TIMER_reg_n_0_[7] ),
        .I2(\TIMER_reg_n_0_[5] ),
        .I3(\TIMER_reg_n_0_[6] ),
        .I4(\TIMER_reg_n_0_[8] ),
        .O(TIMER[8]));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \TIMER[9]_i_1__1 
       (.I0(\TIMER[9]_i_2__1_n_0 ),
        .I1(\TIMER_reg_n_0_[8] ),
        .I2(\TIMER_reg_n_0_[6] ),
        .I3(\TIMER_reg_n_0_[5] ),
        .I4(\TIMER_reg_n_0_[7] ),
        .I5(\TIMER_reg_n_0_[9] ),
        .O(TIMER[9]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \TIMER[9]_i_2__1 
       (.I0(\TIMER_reg_n_0_[3] ),
        .I1(\TIMER_reg_n_0_[1] ),
        .I2(\TIMER_reg_n_0_[0] ),
        .I3(\TIMER_reg_n_0_[2] ),
        .I4(\TIMER_reg_n_0_[4] ),
        .O(\TIMER[9]_i_2__1_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[0]),
        .Q(\TIMER_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[1]),
        .Q(\TIMER_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[2]),
        .Q(\TIMER_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TIMER_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[3]),
        .Q(\TIMER_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TIMER_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[4]),
        .Q(\TIMER_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[5]),
        .Q(\TIMER_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[6]),
        .Q(\TIMER_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[7]),
        .Q(\TIMER_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[8]),
        .Q(\TIMER_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \TIMER_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TIMER[9]),
        .Q(\TIMER_reg_n_0_[9] ),
        .R(1'b0));
endmodule

module RAM32M_UNIQ_BASE_
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD10
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD11
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD12
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD13
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD14
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD4
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD5
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD6
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD7
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD8
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RAM32M" *) 
module RAM32M_HD9
   (DOA,
    DOB,
    DOC,
    DOD,
    ADDRA,
    ADDRB,
    ADDRC,
    ADDRD,
    DIA,
    DIB,
    DIC,
    DID,
    WCLK,
    WE);
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]DOD;
  input [4:0]ADDRA;
  input [4:0]ADDRB;
  input [4:0]ADDRC;
  input [4:0]ADDRD;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [1:0]DID;
  input WCLK;
  input WE;

  wire ADDRA0;
  wire ADDRA1;
  wire ADDRA2;
  wire ADDRA3;
  wire ADDRA4;
  wire ADDRB0;
  wire ADDRB1;
  wire ADDRB2;
  wire ADDRB3;
  wire ADDRB4;
  wire ADDRC0;
  wire ADDRC1;
  wire ADDRC2;
  wire ADDRC3;
  wire ADDRC4;
  wire ADDRD0;
  wire ADDRD1;
  wire ADDRD2;
  wire ADDRD3;
  wire ADDRD4;
  wire DIA0;
  wire DIA1;
  wire DIB0;
  wire DIB1;
  wire DIC0;
  wire DIC1;
  wire DID0;
  wire DID1;
  wire DOA0;
  wire DOA1;
  wire DOB0;
  wire DOB1;
  wire DOC0;
  wire DOC1;
  wire DOD0;
  wire DOD1;
  wire WCLK;
  wire WE;

  assign ADDRA0 = ADDRA[0];
  assign ADDRA1 = ADDRA[1];
  assign ADDRA2 = ADDRA[2];
  assign ADDRA3 = ADDRA[3];
  assign ADDRA4 = ADDRA[4];
  assign ADDRB0 = ADDRB[0];
  assign ADDRB1 = ADDRB[1];
  assign ADDRB2 = ADDRB[2];
  assign ADDRB3 = ADDRB[3];
  assign ADDRB4 = ADDRB[4];
  assign ADDRC0 = ADDRC[0];
  assign ADDRC1 = ADDRC[1];
  assign ADDRC2 = ADDRC[2];
  assign ADDRC3 = ADDRC[3];
  assign ADDRC4 = ADDRC[4];
  assign ADDRD0 = ADDRD[0];
  assign ADDRD1 = ADDRD[1];
  assign ADDRD2 = ADDRD[2];
  assign ADDRD3 = ADDRD[3];
  assign ADDRD4 = ADDRD[4];
  assign DIA0 = DIA[0];
  assign DIA1 = DIA[1];
  assign DIB0 = DIB[0];
  assign DIB1 = DIB[1];
  assign DIC0 = DIC[0];
  assign DIC1 = DIC[1];
  assign DID0 = DID[0];
  assign DID1 = DID[1];
  assign DOA[1] = DOA1;
  assign DOA[0] = DOA0;
  assign DOB[1] = DOB1;
  assign DOB[0] = DOB0;
  assign DOC[1] = DOC1;
  assign DOC[0] = DOC0;
  assign DOD[1] = DOD1;
  assign DOD[0] = DOD0;
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA
       (.CLK(WCLK),
        .I(DIA0),
        .O(DOA0),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMA_D1
       (.CLK(WCLK),
        .I(DIA1),
        .O(DOA1),
        .RADR0(ADDRA0),
        .RADR1(ADDRA1),
        .RADR2(ADDRA2),
        .RADR3(ADDRA3),
        .RADR4(ADDRA4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB
       (.CLK(WCLK),
        .I(DIB0),
        .O(DOB0),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMB_D1
       (.CLK(WCLK),
        .I(DIB1),
        .O(DOB1),
        .RADR0(ADDRB0),
        .RADR1(ADDRB1),
        .RADR2(ADDRB2),
        .RADR3(ADDRB3),
        .RADR4(ADDRB4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC
       (.CLK(WCLK),
        .I(DIC0),
        .O(DOC0),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMD32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMC_D1
       (.CLK(WCLK),
        .I(DIC1),
        .O(DOC1),
        .RADR0(ADDRC0),
        .RADR1(ADDRC1),
        .RADR2(ADDRC2),
        .RADR3(ADDRC3),
        .RADR4(ADDRC4),
        .WADR0(ADDRD0),
        .WADR1(ADDRD1),
        .WADR2(ADDRD2),
        .WADR3(ADDRD3),
        .WADR4(ADDRD4),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID0),
        .O(DOD0),
        .WE(WE));
  RAMS32 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    RAMD_D1
       (.ADR0(ADDRD0),
        .ADR1(ADDRD1),
        .ADR2(ADDRD2),
        .ADR3(ADDRD3),
        .ADR4(ADDRD4),
        .CLK(WCLK),
        .I(DID1),
        .O(DOD1),
        .WE(WE));
endmodule

module SERIAL_INPUT
   (OUT1,
    OUT1_STB,
    INTERNAL_RST_reg,
    ETH_CLK_OBUF,
    OUT1_ACK,
    RX);
  output [7:0]OUT1;
  output OUT1_STB;
  input INTERNAL_RST_reg;
  input ETH_CLK_OBUF;
  input OUT1_ACK;
  input RX;

  wire [11:0]BAUD_COUNT;
  wire \BAUD_COUNT[11]_i_2_n_0 ;
  wire \BAUD_COUNT[11]_i_3_n_0 ;
  wire \BAUD_COUNT[11]_i_5_n_0 ;
  wire \BAUD_COUNT_reg[4]_i_2__0_n_0 ;
  wire \BAUD_COUNT_reg[8]_i_2__0_n_0 ;
  wire \BAUD_COUNT_reg_n_0_[0] ;
  wire \BAUD_COUNT_reg_n_0_[10] ;
  wire \BAUD_COUNT_reg_n_0_[11] ;
  wire \BAUD_COUNT_reg_n_0_[1] ;
  wire \BAUD_COUNT_reg_n_0_[2] ;
  wire \BAUD_COUNT_reg_n_0_[3] ;
  wire \BAUD_COUNT_reg_n_0_[4] ;
  wire \BAUD_COUNT_reg_n_0_[5] ;
  wire \BAUD_COUNT_reg_n_0_[6] ;
  wire \BAUD_COUNT_reg_n_0_[7] ;
  wire \BAUD_COUNT_reg_n_0_[8] ;
  wire \BAUD_COUNT_reg_n_0_[9] ;
  wire \BIT_SPACING[0]_i_1_n_0 ;
  wire \BIT_SPACING[0]_i_2_n_0 ;
  wire \BIT_SPACING[1]_i_1_n_0 ;
  wire \BIT_SPACING[2]_i_1_n_0 ;
  wire \BIT_SPACING[2]_i_2_n_0 ;
  wire \BIT_SPACING[2]_i_3_n_0 ;
  wire \BIT_SPACING[3]_i_1_n_0 ;
  wire \BIT_SPACING[3]_i_2_n_0 ;
  wire \BIT_SPACING[3]_i_3_n_0 ;
  wire \BIT_SPACING[3]_i_4_n_0 ;
  wire \BIT_SPACING[3]_i_5_n_0 ;
  wire \BIT_SPACING_reg_n_0_[0] ;
  wire \BIT_SPACING_reg_n_0_[1] ;
  wire \BIT_SPACING_reg_n_0_[2] ;
  wire \BIT_SPACING_reg_n_0_[3] ;
  wire \COUNT[0]_i_1_n_0 ;
  wire \COUNT[1]_i_1_n_0 ;
  wire \COUNT_reg_n_0_[0] ;
  wire \COUNT_reg_n_0_[1] ;
  wire ETH_CLK_OBUF;
  wire \FSM_sequential_STATE[0]_i_1__0_n_0 ;
  wire \FSM_sequential_STATE[1]_i_1__0_n_0 ;
  wire \FSM_sequential_STATE[2]_i_1__0_n_0 ;
  wire \FSM_sequential_STATE[3]_i_1__0_n_0 ;
  wire \FSM_sequential_STATE[3]_i_2__0_n_0 ;
  wire \FSM_sequential_STATE[3]_i_3__0_n_0 ;
  wire \FSM_sequential_STATE[3]_i_4_n_0 ;
  wire \FSM_sequential_STATE[3]_i_5_n_0 ;
  wire \FSM_sequential_STATE[3]_i_6_n_0 ;
  wire \FSM_sequential_STATE[3]_i_7_n_0 ;
  wire INTERNAL_RST_reg;
  wire INT_SERIAL_i_1_n_0;
  wire INT_SERIAL_reg_n_0;
  wire [7:0]OUT1;
  wire \OUT1[0]_i_1_n_0 ;
  wire \OUT1[1]_i_1_n_0 ;
  wire \OUT1[2]_i_1_n_0 ;
  wire \OUT1[3]_i_1_n_0 ;
  wire \OUT1[3]_i_2_n_0 ;
  wire \OUT1[4]_i_1_n_0 ;
  wire \OUT1[4]_i_2_n_0 ;
  wire \OUT1[5]_i_1_n_0 ;
  wire \OUT1[5]_i_2_n_0 ;
  wire \OUT1[6]_i_1_n_0 ;
  wire \OUT1[7]_i_1_n_0 ;
  wire OUT1_ACK;
  wire OUT1_STB;
  wire OUT1_STB_i_1_n_0;
  wire OUT1_STB_i_2_n_0;
  wire RX;
  (* RTL_KEEP = "yes" *) wire [3:0]STATE;
  wire X16CLK_EN7_out;
  wire X16CLK_EN_reg_n_0;
  wire [11:1]data0;
  wire p_0_in;
  wire p_0_in3_in;
  wire [1:1]p_0_in__0;
  wire [3:0]\NLW_BAUD_COUNT_reg[11]_i_4__0_CO_UNCONNECTED ;
  wire [3:3]\NLW_BAUD_COUNT_reg[11]_i_4__0_O_UNCONNECTED ;
  wire [2:0]\NLW_BAUD_COUNT_reg[4]_i_2__0_CO_UNCONNECTED ;
  wire [2:0]\NLW_BAUD_COUNT_reg[8]_i_2__0_CO_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \BAUD_COUNT[0]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(\BAUD_COUNT_reg_n_0_[0] ),
        .O(BAUD_COUNT[0]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[10]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[10]),
        .O(BAUD_COUNT[10]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[11]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[11]),
        .O(BAUD_COUNT[11]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \BAUD_COUNT[11]_i_2 
       (.I0(\BAUD_COUNT_reg_n_0_[10] ),
        .I1(\BAUD_COUNT_reg_n_0_[11] ),
        .I2(\BAUD_COUNT_reg_n_0_[9] ),
        .I3(\BAUD_COUNT_reg_n_0_[8] ),
        .I4(\BAUD_COUNT_reg_n_0_[7] ),
        .O(\BAUD_COUNT[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0707FF07)) 
    \BAUD_COUNT[11]_i_3 
       (.I0(\BAUD_COUNT_reg_n_0_[4] ),
        .I1(\BAUD_COUNT_reg_n_0_[3] ),
        .I2(\BAUD_COUNT_reg_n_0_[5] ),
        .I3(\BAUD_COUNT_reg_n_0_[6] ),
        .I4(\BAUD_COUNT_reg_n_0_[7] ),
        .I5(\BAUD_COUNT[11]_i_5_n_0 ),
        .O(\BAUD_COUNT[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDFFFFFFFFFFFF)) 
    \BAUD_COUNT[11]_i_5 
       (.I0(\BAUD_COUNT_reg_n_0_[4] ),
        .I1(\BAUD_COUNT_reg_n_0_[8] ),
        .I2(\BAUD_COUNT_reg_n_0_[5] ),
        .I3(\BAUD_COUNT_reg_n_0_[2] ),
        .I4(\BAUD_COUNT_reg_n_0_[0] ),
        .I5(\BAUD_COUNT_reg_n_0_[1] ),
        .O(\BAUD_COUNT[11]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[1]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[1]),
        .O(BAUD_COUNT[1]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[2]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[2]),
        .O(BAUD_COUNT[2]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[3]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[3]),
        .O(BAUD_COUNT[3]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[4]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[4]),
        .O(BAUD_COUNT[4]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[5]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[5]),
        .O(BAUD_COUNT[5]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[6]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[6]),
        .O(BAUD_COUNT[6]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[7]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[7]),
        .O(BAUD_COUNT[7]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[8]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[8]),
        .O(BAUD_COUNT[8]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[9]_i_1 
       (.I0(\BAUD_COUNT[11]_i_2_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3_n_0 ),
        .I2(data0[9]),
        .O(BAUD_COUNT[9]));
  FDRE \BAUD_COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[0]),
        .Q(\BAUD_COUNT_reg_n_0_[0] ),
        .R(INTERNAL_RST_reg));
  FDRE \BAUD_COUNT_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[10]),
        .Q(\BAUD_COUNT_reg_n_0_[10] ),
        .R(INTERNAL_RST_reg));
  FDRE \BAUD_COUNT_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[11]),
        .Q(\BAUD_COUNT_reg_n_0_[11] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \BAUD_COUNT_reg[11]_i_4__0 
       (.CI(\BAUD_COUNT_reg[8]_i_2__0_n_0 ),
        .CO(\NLW_BAUD_COUNT_reg[11]_i_4__0_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_BAUD_COUNT_reg[11]_i_4__0_O_UNCONNECTED [3],data0[11:9]}),
        .S({1'b0,\BAUD_COUNT_reg_n_0_[11] ,\BAUD_COUNT_reg_n_0_[10] ,\BAUD_COUNT_reg_n_0_[9] }));
  FDRE \BAUD_COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[1]),
        .Q(\BAUD_COUNT_reg_n_0_[1] ),
        .R(INTERNAL_RST_reg));
  FDRE \BAUD_COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[2]),
        .Q(\BAUD_COUNT_reg_n_0_[2] ),
        .R(INTERNAL_RST_reg));
  FDRE \BAUD_COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[3]),
        .Q(\BAUD_COUNT_reg_n_0_[3] ),
        .R(INTERNAL_RST_reg));
  FDRE \BAUD_COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[4]),
        .Q(\BAUD_COUNT_reg_n_0_[4] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \BAUD_COUNT_reg[4]_i_2__0 
       (.CI(1'b0),
        .CO({\BAUD_COUNT_reg[4]_i_2__0_n_0 ,\NLW_BAUD_COUNT_reg[4]_i_2__0_CO_UNCONNECTED [2:0]}),
        .CYINIT(\BAUD_COUNT_reg_n_0_[0] ),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data0[4:1]),
        .S({\BAUD_COUNT_reg_n_0_[4] ,\BAUD_COUNT_reg_n_0_[3] ,\BAUD_COUNT_reg_n_0_[2] ,\BAUD_COUNT_reg_n_0_[1] }));
  FDRE \BAUD_COUNT_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[5]),
        .Q(\BAUD_COUNT_reg_n_0_[5] ),
        .R(INTERNAL_RST_reg));
  FDRE \BAUD_COUNT_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[6]),
        .Q(\BAUD_COUNT_reg_n_0_[6] ),
        .R(INTERNAL_RST_reg));
  FDRE \BAUD_COUNT_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[7]),
        .Q(\BAUD_COUNT_reg_n_0_[7] ),
        .R(INTERNAL_RST_reg));
  FDRE \BAUD_COUNT_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[8]),
        .Q(\BAUD_COUNT_reg_n_0_[8] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \BAUD_COUNT_reg[8]_i_2__0 
       (.CI(\BAUD_COUNT_reg[4]_i_2__0_n_0 ),
        .CO({\BAUD_COUNT_reg[8]_i_2__0_n_0 ,\NLW_BAUD_COUNT_reg[8]_i_2__0_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data0[8:5]),
        .S({\BAUD_COUNT_reg_n_0_[8] ,\BAUD_COUNT_reg_n_0_[7] ,\BAUD_COUNT_reg_n_0_[6] ,\BAUD_COUNT_reg_n_0_[5] }));
  FDRE \BAUD_COUNT_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[9]),
        .Q(\BAUD_COUNT_reg_n_0_[9] ),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'h3222332232223222)) 
    \BIT_SPACING[0]_i_1 
       (.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
        .I1(\BIT_SPACING_reg_n_0_[0] ),
        .I2(\BIT_SPACING[3]_i_4_n_0 ),
        .I3(\BIT_SPACING[0]_i_2_n_0 ),
        .I4(p_0_in),
        .I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
        .O(\BIT_SPACING[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \BIT_SPACING[0]_i_2 
       (.I0(\BIT_SPACING_reg_n_0_[3] ),
        .I1(\BIT_SPACING_reg_n_0_[2] ),
        .I2(\BIT_SPACING_reg_n_0_[0] ),
        .I3(\BIT_SPACING_reg_n_0_[1] ),
        .O(\BIT_SPACING[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6660666666606660)) 
    \BIT_SPACING[1]_i_1 
       (.I0(\BIT_SPACING_reg_n_0_[1] ),
        .I1(\BIT_SPACING_reg_n_0_[0] ),
        .I2(\FSM_sequential_STATE[3]_i_4_n_0 ),
        .I3(\BIT_SPACING[3]_i_4_n_0 ),
        .I4(p_0_in),
        .I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
        .O(\BIT_SPACING[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF888FF88F888F888)) 
    \BIT_SPACING[2]_i_1 
       (.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
        .I1(\BIT_SPACING[2]_i_2_n_0 ),
        .I2(\BIT_SPACING[3]_i_4_n_0 ),
        .I3(\BIT_SPACING[2]_i_3_n_0 ),
        .I4(p_0_in),
        .I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
        .O(\BIT_SPACING[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h6C)) 
    \BIT_SPACING[2]_i_2 
       (.I0(\BIT_SPACING_reg_n_0_[1] ),
        .I1(\BIT_SPACING_reg_n_0_[2] ),
        .I2(\BIT_SPACING_reg_n_0_[0] ),
        .O(\BIT_SPACING[2]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \BIT_SPACING[2]_i_3 
       (.I0(\BIT_SPACING_reg_n_0_[1] ),
        .I1(\BIT_SPACING_reg_n_0_[0] ),
        .I2(\BIT_SPACING_reg_n_0_[2] ),
        .O(\BIT_SPACING[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h55FF0001)) 
    \BIT_SPACING[3]_i_1 
       (.I0(STATE[3]),
        .I1(STATE[0]),
        .I2(STATE[1]),
        .I3(STATE[2]),
        .I4(X16CLK_EN_reg_n_0),
        .O(\BIT_SPACING[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF888FF88F888F888)) 
    \BIT_SPACING[3]_i_2 
       (.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
        .I1(\BIT_SPACING[3]_i_3_n_0 ),
        .I2(\BIT_SPACING[3]_i_4_n_0 ),
        .I3(\BIT_SPACING[3]_i_5_n_0 ),
        .I4(p_0_in),
        .I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
        .O(\BIT_SPACING[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h52F0F0F0)) 
    \BIT_SPACING[3]_i_3 
       (.I0(\BIT_SPACING_reg_n_0_[1] ),
        .I1(X16CLK_EN_reg_n_0),
        .I2(\BIT_SPACING_reg_n_0_[3] ),
        .I3(\BIT_SPACING_reg_n_0_[2] ),
        .I4(\BIT_SPACING_reg_n_0_[0] ),
        .O(\BIT_SPACING[3]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \BIT_SPACING[3]_i_4 
       (.I0(STATE[2]),
        .I1(STATE[3]),
        .I2(STATE[1]),
        .I3(STATE[0]),
        .O(\BIT_SPACING[3]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \BIT_SPACING[3]_i_5 
       (.I0(\BIT_SPACING_reg_n_0_[1] ),
        .I1(\BIT_SPACING_reg_n_0_[0] ),
        .I2(\BIT_SPACING_reg_n_0_[2] ),
        .I3(\BIT_SPACING_reg_n_0_[3] ),
        .O(\BIT_SPACING[3]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \BIT_SPACING[3]_i_6 
       (.I0(\BIT_SPACING_reg_n_0_[3] ),
        .I1(\BIT_SPACING_reg_n_0_[1] ),
        .I2(\BIT_SPACING_reg_n_0_[0] ),
        .I3(\BIT_SPACING_reg_n_0_[2] ),
        .I4(X16CLK_EN_reg_n_0),
        .O(p_0_in));
  FDRE \BIT_SPACING_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\BIT_SPACING[3]_i_1_n_0 ),
        .D(\BIT_SPACING[0]_i_1_n_0 ),
        .Q(\BIT_SPACING_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \BIT_SPACING_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\BIT_SPACING[3]_i_1_n_0 ),
        .D(\BIT_SPACING[1]_i_1_n_0 ),
        .Q(\BIT_SPACING_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \BIT_SPACING_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\BIT_SPACING[3]_i_1_n_0 ),
        .D(\BIT_SPACING[2]_i_1_n_0 ),
        .Q(\BIT_SPACING_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \BIT_SPACING_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\BIT_SPACING[3]_i_1_n_0 ),
        .D(\BIT_SPACING[3]_i_2_n_0 ),
        .Q(\BIT_SPACING_reg_n_0_[3] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8FE0)) 
    \COUNT[0]_i_1 
       (.I0(p_0_in3_in),
        .I1(\COUNT_reg_n_0_[1] ),
        .I2(X16CLK_EN_reg_n_0),
        .I3(\COUNT_reg_n_0_[0] ),
        .O(\COUNT[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'hECC4)) 
    \COUNT[1]_i_1 
       (.I0(X16CLK_EN_reg_n_0),
        .I1(\COUNT_reg_n_0_[1] ),
        .I2(p_0_in3_in),
        .I3(\COUNT_reg_n_0_[0] ),
        .O(\COUNT[1]_i_1_n_0 ));
  FDRE \COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\COUNT[0]_i_1_n_0 ),
        .Q(\COUNT_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\COUNT[1]_i_1_n_0 ),
        .Q(\COUNT_reg_n_0_[1] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h07)) 
    \FSM_sequential_STATE[0]_i_1__0 
       (.I0(STATE[2]),
        .I1(STATE[3]),
        .I2(STATE[0]),
        .O(\FSM_sequential_STATE[0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h152A)) 
    \FSM_sequential_STATE[1]_i_1__0 
       (.I0(STATE[1]),
        .I1(STATE[2]),
        .I2(STATE[3]),
        .I3(STATE[0]),
        .O(\FSM_sequential_STATE[1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h006A)) 
    \FSM_sequential_STATE[2]_i_1__0 
       (.I0(STATE[2]),
        .I1(STATE[1]),
        .I2(STATE[0]),
        .I3(STATE[3]),
        .O(\FSM_sequential_STATE[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFA8FF20)) 
    \FSM_sequential_STATE[3]_i_1__0 
       (.I0(\FSM_sequential_STATE[3]_i_3__0_n_0 ),
        .I1(\BIT_SPACING_reg_n_0_[3] ),
        .I2(\FSM_sequential_STATE[3]_i_4_n_0 ),
        .I3(\FSM_sequential_STATE[3]_i_5_n_0 ),
        .I4(\FSM_sequential_STATE[3]_i_6_n_0 ),
        .I5(\FSM_sequential_STATE[3]_i_7_n_0 ),
        .O(\FSM_sequential_STATE[3]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h1580)) 
    \FSM_sequential_STATE[3]_i_2__0 
       (.I0(STATE[2]),
        .I1(STATE[1]),
        .I2(STATE[0]),
        .I3(STATE[3]),
        .O(\FSM_sequential_STATE[3]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \FSM_sequential_STATE[3]_i_3__0 
       (.I0(X16CLK_EN_reg_n_0),
        .I1(\BIT_SPACING_reg_n_0_[2] ),
        .I2(\BIT_SPACING_reg_n_0_[0] ),
        .I3(\BIT_SPACING_reg_n_0_[1] ),
        .O(\FSM_sequential_STATE[3]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \FSM_sequential_STATE[3]_i_4 
       (.I0(STATE[3]),
        .I1(STATE[0]),
        .I2(STATE[2]),
        .I3(STATE[1]),
        .O(\FSM_sequential_STATE[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \FSM_sequential_STATE[3]_i_5 
       (.I0(STATE[1]),
        .I1(STATE[2]),
        .I2(X16CLK_EN_reg_n_0),
        .I3(INT_SERIAL_reg_n_0),
        .I4(STATE[3]),
        .I5(STATE[0]),
        .O(\FSM_sequential_STATE[3]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h337C)) 
    \FSM_sequential_STATE[3]_i_6 
       (.I0(STATE[0]),
        .I1(STATE[3]),
        .I2(STATE[1]),
        .I3(STATE[2]),
        .O(\FSM_sequential_STATE[3]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h00800000)) 
    \FSM_sequential_STATE[3]_i_7 
       (.I0(STATE[0]),
        .I1(STATE[1]),
        .I2(STATE[3]),
        .I3(STATE[2]),
        .I4(OUT1_ACK),
        .O(\FSM_sequential_STATE[3]_i_7_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_STATE_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
        .D(\FSM_sequential_STATE[0]_i_1__0_n_0 ),
        .Q(STATE[0]),
        .R(INTERNAL_RST_reg));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_STATE_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
        .D(\FSM_sequential_STATE[1]_i_1__0_n_0 ),
        .Q(STATE[1]),
        .R(INTERNAL_RST_reg));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_STATE_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
        .D(\FSM_sequential_STATE[2]_i_1__0_n_0 ),
        .Q(STATE[2]),
        .R(INTERNAL_RST_reg));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_STATE_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
        .D(\FSM_sequential_STATE[3]_i_2__0_n_0 ),
        .Q(STATE[3]),
        .R(INTERNAL_RST_reg));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT5 #(
    .INIT(32'hEAAAA8AA)) 
    INT_SERIAL_i_1
       (.I0(INT_SERIAL_reg_n_0),
        .I1(\COUNT_reg_n_0_[1] ),
        .I2(\COUNT_reg_n_0_[0] ),
        .I3(X16CLK_EN_reg_n_0),
        .I4(p_0_in3_in),
        .O(INT_SERIAL_i_1_n_0));
  FDRE INT_SERIAL_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(INT_SERIAL_i_1_n_0),
        .Q(INT_SERIAL_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFBFFFFF00800000)) 
    \OUT1[0]_i_1 
       (.I0(INT_SERIAL_reg_n_0),
        .I1(p_0_in),
        .I2(STATE[1]),
        .I3(STATE[2]),
        .I4(\OUT1[4]_i_2_n_0 ),
        .I5(OUT1[0]),
        .O(\OUT1[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF8FFFFFF08000000)) 
    \OUT1[1]_i_1 
       (.I0(INT_SERIAL_reg_n_0),
        .I1(\OUT1[3]_i_2_n_0 ),
        .I2(STATE[2]),
        .I3(p_0_in),
        .I4(\OUT1[5]_i_2_n_0 ),
        .I5(OUT1[1]),
        .O(\OUT1[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFFFFF00800000)) 
    \OUT1[2]_i_1 
       (.I0(INT_SERIAL_reg_n_0),
        .I1(STATE[2]),
        .I2(\OUT1[4]_i_2_n_0 ),
        .I3(STATE[1]),
        .I4(p_0_in),
        .I5(OUT1[2]),
        .O(\OUT1[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFFFFF00800000)) 
    \OUT1[3]_i_1 
       (.I0(INT_SERIAL_reg_n_0),
        .I1(STATE[2]),
        .I2(\OUT1[3]_i_2_n_0 ),
        .I3(STATE[1]),
        .I4(p_0_in),
        .I5(OUT1[3]),
        .O(\OUT1[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \OUT1[3]_i_2 
       (.I0(STATE[0]),
        .I1(STATE[3]),
        .O(\OUT1[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFFFFF80000000)) 
    \OUT1[4]_i_1 
       (.I0(INT_SERIAL_reg_n_0),
        .I1(p_0_in),
        .I2(STATE[1]),
        .I3(STATE[2]),
        .I4(\OUT1[4]_i_2_n_0 ),
        .I5(OUT1[4]),
        .O(\OUT1[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \OUT1[4]_i_2 
       (.I0(STATE[0]),
        .I1(STATE[3]),
        .O(\OUT1[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \OUT1[5]_i_1 
       (.I0(INT_SERIAL_reg_n_0),
        .I1(STATE[2]),
        .I2(p_0_in),
        .I3(\OUT1[5]_i_2_n_0 ),
        .I4(OUT1[5]),
        .O(\OUT1[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \OUT1[5]_i_2 
       (.I0(STATE[1]),
        .I1(STATE[0]),
        .I2(STATE[3]),
        .O(\OUT1[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFF00200000)) 
    \OUT1[6]_i_1 
       (.I0(INT_SERIAL_reg_n_0),
        .I1(STATE[0]),
        .I2(STATE[3]),
        .I3(STATE[1]),
        .I4(p_0_in),
        .I5(OUT1[6]),
        .O(\OUT1[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFFFFF00800000)) 
    \OUT1[7]_i_1 
       (.I0(INT_SERIAL_reg_n_0),
        .I1(STATE[3]),
        .I2(STATE[0]),
        .I3(STATE[1]),
        .I4(p_0_in),
        .I5(OUT1[7]),
        .O(\OUT1[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h10FF1000)) 
    OUT1_STB_i_1
       (.I0(STATE[2]),
        .I1(STATE[0]),
        .I2(p_0_in),
        .I3(OUT1_STB_i_2_n_0),
        .I4(OUT1_STB),
        .O(OUT1_STB_i_1_n_0));
  LUT6 #(
    .INIT(64'h080C000008000000)) 
    OUT1_STB_i_2
       (.I0(OUT1_ACK),
        .I1(STATE[3]),
        .I2(STATE[2]),
        .I3(STATE[0]),
        .I4(STATE[1]),
        .I5(p_0_in),
        .O(OUT1_STB_i_2_n_0));
  FDRE OUT1_STB_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(OUT1_STB_i_1_n_0),
        .Q(OUT1_STB),
        .R(INTERNAL_RST_reg));
  FDRE \OUT1_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\OUT1[0]_i_1_n_0 ),
        .Q(OUT1[0]),
        .R(1'b0));
  FDRE \OUT1_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\OUT1[1]_i_1_n_0 ),
        .Q(OUT1[1]),
        .R(1'b0));
  FDRE \OUT1_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\OUT1[2]_i_1_n_0 ),
        .Q(OUT1[2]),
        .R(1'b0));
  FDRE \OUT1_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\OUT1[3]_i_1_n_0 ),
        .Q(OUT1[3]),
        .R(1'b0));
  FDRE \OUT1_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\OUT1[4]_i_1_n_0 ),
        .Q(OUT1[4]),
        .R(1'b0));
  FDRE \OUT1_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\OUT1[5]_i_1_n_0 ),
        .Q(OUT1[5]),
        .R(1'b0));
  FDRE \OUT1_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\OUT1[6]_i_1_n_0 ),
        .Q(OUT1[6]),
        .R(1'b0));
  FDRE \OUT1_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\OUT1[7]_i_1_n_0 ),
        .Q(OUT1[7]),
        .R(1'b0));
  FDSE \SERIAL_DEGLITCH_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(RX),
        .Q(p_0_in__0),
        .S(INTERNAL_RST_reg));
  FDSE \SERIAL_DEGLITCH_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(p_0_in__0),
        .Q(p_0_in3_in),
        .S(INTERNAL_RST_reg));
  LUT3 #(
    .INIT(8'h01)) 
    X16CLK_EN_i_1
       (.I0(INTERNAL_RST_reg),
        .I1(\BAUD_COUNT[11]_i_2_n_0 ),
        .I2(\BAUD_COUNT[11]_i_3_n_0 ),
        .O(X16CLK_EN7_out));
  FDRE X16CLK_EN_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(X16CLK_EN7_out),
        .Q(X16CLK_EN_reg_n_0),
        .R(1'b0));
endmodule

module VIDEO_TIME_GEN
   (\PIXCOL_DEL_reg[0] ,
    \PIXCOL_DEL_reg[1] ,
    \PIXCOL_DEL_reg[2] ,
    ADDRBWRADDR,
    \PIXROW_DEL_reg[0] ,
    \PIXROW_DEL_reg[1] ,
    D,
    HSYNCH_DEL_reg,
    VSYNCH_DEL_reg,
    BLANK,
    ETH_CLK_OBUF,
    INTERNAL_RST_reg);
  output \PIXCOL_DEL_reg[0] ;
  output \PIXCOL_DEL_reg[1] ;
  output \PIXCOL_DEL_reg[2] ;
  output [12:0]ADDRBWRADDR;
  output \PIXROW_DEL_reg[0] ;
  output \PIXROW_DEL_reg[1] ;
  output [0:0]D;
  output HSYNCH_DEL_reg;
  output VSYNCH_DEL_reg;
  output BLANK;
  input ETH_CLK_OBUF;
  input INTERNAL_RST_reg;

  wire [12:0]ADDRBWRADDR;
  wire BLANK;
  wire \COL_ADDRESS[0]_i_1_n_0 ;
  wire \COL_ADDRESS[1]_i_1_n_0 ;
  wire \COL_ADDRESS[2]_i_1_n_0 ;
  wire \COL_ADDRESS[3]_i_1_n_0 ;
  wire \COL_ADDRESS[4]_i_1_n_0 ;
  wire \COL_ADDRESS[5]_i_1_n_0 ;
  wire \COL_ADDRESS[6]_i_1_n_0 ;
  wire \COL_ADDRESS[6]_i_2_n_0 ;
  wire \COL_ADDRESS[6]_i_3_n_0 ;
  wire \COL_ADDRESS_reg_n_0_[1] ;
  wire \COL_ADDRESS_reg_n_0_[2] ;
  wire \COL_ADDRESS_reg_n_0_[3] ;
  wire \COL_ADDRESS_reg_n_0_[4] ;
  wire \COL_ADDRESS_reg_n_0_[5] ;
  wire \COL_ADDRESS_reg_n_0_[6] ;
  wire [0:0]D;
  wire ETH_CLK_OBUF;
  wire HBLANK_i_1_n_0;
  wire HBLANK_i_2_n_0;
  wire HBLANK_i_3_n_0;
  wire HBLANK_i_4_n_0;
  wire HBLANK_i_5_n_0;
  wire HBLANK_i_6_n_0;
  wire HBLANK_reg_n_0;
  wire HSYNCH_DEL_reg;
  wire [10:0]HTIMER;
  wire \HTIMER[0]_i_2_n_0 ;
  wire \HTIMER[0]_i_3_n_0 ;
  wire \HTIMER[10]_i_2_n_0 ;
  wire \HTIMER[10]_i_3_n_0 ;
  wire \HTIMER[10]_i_4_n_0 ;
  wire \HTIMER[2]_i_1_n_0 ;
  wire \HTIMER[4]_i_2_n_0 ;
  wire \HTIMER[5]_i_1_n_0 ;
  wire \HTIMER[6]_i_1_n_0 ;
  wire \HTIMER[9]_i_2_n_0 ;
  wire INTERNAL_RST_reg;
  wire INTHSYNCH_i_1_n_0;
  wire INTVSYNCH2_out;
  wire INTVSYNCH_i_1_n_0;
  wire INTVSYNCH_i_3_n_0;
  wire MEMORY_reg_0_i_11_n_0;
  wire MEMORY_reg_0_i_12_n_0;
  wire MEMORY_reg_0_i_13_n_0;
  wire MEMORY_reg_0_i_14_n_0;
  wire MEMORY_reg_0_i_15_n_0;
  wire MEMORY_reg_0_i_16_n_0;
  wire MEMORY_reg_0_i_2_n_0;
  wire MEMORY_reg_0_i_3_n_0;
  wire \PIXCOL_DEL_reg[0] ;
  wire \PIXCOL_DEL_reg[1] ;
  wire \PIXCOL_DEL_reg[2] ;
  wire \PIXROW_DEL_reg[0] ;
  wire \PIXROW_DEL_reg[1] ;
  wire \PIX_COL_ADDRESS[0]_i_1_n_0 ;
  wire \PIX_COL_ADDRESS[1]_i_1_n_0 ;
  wire \PIX_COL_ADDRESS[2]_i_1_n_0 ;
  wire \PIX_ROW_ADDRESS[0]_i_1_n_0 ;
  wire \PIX_ROW_ADDRESS[1]_i_1_n_0 ;
  wire \PIX_ROW_ADDRESS[2]_i_1_n_0 ;
  wire \PIX_ROW_ADDRESS[2]_i_2_n_0 ;
  wire \PIX_ROW_ADDRESS[2]_i_3_n_0 ;
  wire [12:1]ROW_ADDRESS;
  wire \ROW_ADDRESS[12]_i_1_n_0 ;
  wire \ROW_ADDRESS[12]_i_3_n_0 ;
  wire \ROW_ADDRESS[12]_i_4_n_0 ;
  wire \ROW_ADDRESS[4]_i_5_n_0 ;
  wire \ROW_ADDRESS[8]_i_5_n_0 ;
  wire \ROW_ADDRESS[8]_i_6_n_0 ;
  wire [12:1]ROW_ADDRESS_0;
  wire \ROW_ADDRESS_reg[12]_i_5_n_4 ;
  wire \ROW_ADDRESS_reg[12]_i_5_n_5 ;
  wire \ROW_ADDRESS_reg[12]_i_5_n_6 ;
  wire \ROW_ADDRESS_reg[12]_i_5_n_7 ;
  wire \ROW_ADDRESS_reg[4]_i_2_n_0 ;
  wire \ROW_ADDRESS_reg[4]_i_2_n_4 ;
  wire \ROW_ADDRESS_reg[4]_i_2_n_5 ;
  wire \ROW_ADDRESS_reg[4]_i_2_n_6 ;
  wire \ROW_ADDRESS_reg[4]_i_2_n_7 ;
  wire \ROW_ADDRESS_reg[8]_i_2_n_0 ;
  wire \ROW_ADDRESS_reg[8]_i_2_n_4 ;
  wire \ROW_ADDRESS_reg[8]_i_2_n_5 ;
  wire \ROW_ADDRESS_reg[8]_i_2_n_6 ;
  wire \ROW_ADDRESS_reg[8]_i_2_n_7 ;
  wire VBLANK_i_1_n_0;
  wire VBLANK_i_2_n_0;
  wire VBLANK_i_3_n_0;
  wire VBLANK_i_4_n_0;
  wire VBLANK_i_5_n_0;
  wire VBLANK_i_6_n_0;
  wire VBLANK_i_7_n_0;
  wire VBLANK_reg_n_0;
  wire VSYNCH_DEL_reg;
  wire [9:0]VTIMER;
  wire \VTIMER[0]_i_1_n_0 ;
  wire \VTIMER[2]_i_2_n_0 ;
  wire \VTIMER[2]_i_3_n_0 ;
  wire \VTIMER[5]_i_1_n_0 ;
  wire \VTIMER[9]_i_2_n_0 ;
  wire \VTIMER[9]_i_3_n_0 ;
  wire \VTIMER[9]_i_4_n_0 ;
  wire \VTIMER[9]_i_5_n_0 ;
  wire [9:1]VTIMER_1;
  wire VTIMER_EN;
  wire VTIMER_EN_i_1_n_0;
  wire [10:0]sel0;
  wire [3:0]NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED;
  wire [2:0]NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED;
  wire [2:0]NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED;
  wire [0:0]NLW_MEMORY_reg_0_i_3_O_UNCONNECTED;
  wire [3:0]\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED ;
  wire [2:0]\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED ;
  wire [2:0]\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED ;

  LUT2 #(
    .INIT(4'hE)) 
    BLANK_DEL_i_1
       (.I0(VBLANK_reg_n_0),
        .I1(HBLANK_reg_n_0),
        .O(BLANK));
  LUT1 #(
    .INIT(2'h1)) 
    \COL_ADDRESS[0]_i_1 
       (.I0(ADDRBWRADDR[0]),
        .O(\COL_ADDRESS[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COL_ADDRESS[1]_i_1 
       (.I0(\COL_ADDRESS_reg_n_0_[1] ),
        .I1(ADDRBWRADDR[0]),
        .O(\COL_ADDRESS[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF00000000EFFF)) 
    \COL_ADDRESS[2]_i_1 
       (.I0(\COL_ADDRESS_reg_n_0_[4] ),
        .I1(\COL_ADDRESS_reg_n_0_[3] ),
        .I2(\COL_ADDRESS_reg_n_0_[6] ),
        .I3(\COL_ADDRESS_reg_n_0_[5] ),
        .I4(\COL_ADDRESS[6]_i_3_n_0 ),
        .I5(\COL_ADDRESS_reg_n_0_[2] ),
        .O(\COL_ADDRESS[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \COL_ADDRESS[3]_i_1 
       (.I0(\COL_ADDRESS_reg_n_0_[3] ),
        .I1(\COL_ADDRESS_reg_n_0_[1] ),
        .I2(ADDRBWRADDR[0]),
        .I3(\COL_ADDRESS_reg_n_0_[2] ),
        .O(\COL_ADDRESS[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \COL_ADDRESS[4]_i_1 
       (.I0(\COL_ADDRESS_reg_n_0_[4] ),
        .I1(\COL_ADDRESS_reg_n_0_[2] ),
        .I2(ADDRBWRADDR[0]),
        .I3(\COL_ADDRESS_reg_n_0_[1] ),
        .I4(\COL_ADDRESS_reg_n_0_[3] ),
        .O(\COL_ADDRESS[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF3FFFFD00C00000)) 
    \COL_ADDRESS[5]_i_1 
       (.I0(\COL_ADDRESS_reg_n_0_[6] ),
        .I1(\COL_ADDRESS_reg_n_0_[4] ),
        .I2(\COL_ADDRESS_reg_n_0_[2] ),
        .I3(\COL_ADDRESS[6]_i_3_n_0 ),
        .I4(\COL_ADDRESS_reg_n_0_[3] ),
        .I5(\COL_ADDRESS_reg_n_0_[5] ),
        .O(\COL_ADDRESS[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000080)) 
    \COL_ADDRESS[6]_i_1 
       (.I0(\PIXCOL_DEL_reg[0] ),
        .I1(\PIXCOL_DEL_reg[1] ),
        .I2(\PIXCOL_DEL_reg[2] ),
        .I3(HBLANK_reg_n_0),
        .I4(VBLANK_reg_n_0),
        .O(\COL_ADDRESS[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFEFFFF20000000)) 
    \COL_ADDRESS[6]_i_2 
       (.I0(\COL_ADDRESS_reg_n_0_[3] ),
        .I1(\COL_ADDRESS[6]_i_3_n_0 ),
        .I2(\COL_ADDRESS_reg_n_0_[2] ),
        .I3(\COL_ADDRESS_reg_n_0_[4] ),
        .I4(\COL_ADDRESS_reg_n_0_[5] ),
        .I5(\COL_ADDRESS_reg_n_0_[6] ),
        .O(\COL_ADDRESS[6]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \COL_ADDRESS[6]_i_3 
       (.I0(\COL_ADDRESS_reg_n_0_[1] ),
        .I1(ADDRBWRADDR[0]),
        .O(\COL_ADDRESS[6]_i_3_n_0 ));
  FDRE \COL_ADDRESS_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\COL_ADDRESS[6]_i_1_n_0 ),
        .D(\COL_ADDRESS[0]_i_1_n_0 ),
        .Q(ADDRBWRADDR[0]),
        .R(INTERNAL_RST_reg));
  FDRE \COL_ADDRESS_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\COL_ADDRESS[6]_i_1_n_0 ),
        .D(\COL_ADDRESS[1]_i_1_n_0 ),
        .Q(\COL_ADDRESS_reg_n_0_[1] ),
        .R(INTERNAL_RST_reg));
  FDRE \COL_ADDRESS_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\COL_ADDRESS[6]_i_1_n_0 ),
        .D(\COL_ADDRESS[2]_i_1_n_0 ),
        .Q(\COL_ADDRESS_reg_n_0_[2] ),
        .R(INTERNAL_RST_reg));
  FDRE \COL_ADDRESS_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\COL_ADDRESS[6]_i_1_n_0 ),
        .D(\COL_ADDRESS[3]_i_1_n_0 ),
        .Q(\COL_ADDRESS_reg_n_0_[3] ),
        .R(INTERNAL_RST_reg));
  FDRE \COL_ADDRESS_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\COL_ADDRESS[6]_i_1_n_0 ),
        .D(\COL_ADDRESS[4]_i_1_n_0 ),
        .Q(\COL_ADDRESS_reg_n_0_[4] ),
        .R(INTERNAL_RST_reg));
  FDRE \COL_ADDRESS_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\COL_ADDRESS[6]_i_1_n_0 ),
        .D(\COL_ADDRESS[5]_i_1_n_0 ),
        .Q(\COL_ADDRESS_reg_n_0_[5] ),
        .R(INTERNAL_RST_reg));
  FDRE \COL_ADDRESS_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\COL_ADDRESS[6]_i_1_n_0 ),
        .D(\COL_ADDRESS[6]_i_2_n_0 ),
        .Q(\COL_ADDRESS_reg_n_0_[6] ),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF70000)) 
    HBLANK_i_1
       (.I0(HBLANK_i_2_n_0),
        .I1(sel0[7]),
        .I2(sel0[8]),
        .I3(sel0[6]),
        .I4(HBLANK_reg_n_0),
        .I5(HBLANK_i_3_n_0),
        .O(HBLANK_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    HBLANK_i_2
       (.I0(sel0[9]),
        .I1(sel0[10]),
        .I2(sel0[5]),
        .I3(sel0[4]),
        .I4(sel0[3]),
        .I5(HBLANK_i_4_n_0),
        .O(HBLANK_i_2_n_0));
  LUT6 #(
    .INIT(64'hAAAAABAAAAAAAAAA)) 
    HBLANK_i_3
       (.I0(INTERNAL_RST_reg),
        .I1(HBLANK_i_5_n_0),
        .I2(sel0[0]),
        .I3(sel0[3]),
        .I4(HBLANK_i_6_n_0),
        .I5(\HTIMER[0]_i_3_n_0 ),
        .O(HBLANK_i_3_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    HBLANK_i_4
       (.I0(sel0[2]),
        .I1(sel0[1]),
        .I2(sel0[0]),
        .O(HBLANK_i_4_n_0));
  LUT3 #(
    .INIT(8'hBF)) 
    HBLANK_i_5
       (.I0(sel0[10]),
        .I1(sel0[8]),
        .I2(sel0[9]),
        .O(HBLANK_i_5_n_0));
  LUT2 #(
    .INIT(4'h7)) 
    HBLANK_i_6
       (.I0(sel0[7]),
        .I1(sel0[6]),
        .O(HBLANK_i_6_n_0));
  FDRE HBLANK_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HBLANK_i_1_n_0),
        .Q(HBLANK_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000FDFF)) 
    \HTIMER[0]_i_1 
       (.I0(\HTIMER[0]_i_2_n_0 ),
        .I1(sel0[6]),
        .I2(sel0[3]),
        .I3(\HTIMER[0]_i_3_n_0 ),
        .I4(sel0[0]),
        .O(HTIMER[0]));
  LUT4 #(
    .INIT(16'h0010)) 
    \HTIMER[0]_i_2 
       (.I0(sel0[8]),
        .I1(sel0[7]),
        .I2(sel0[10]),
        .I3(sel0[9]),
        .O(\HTIMER[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \HTIMER[0]_i_3 
       (.I0(sel0[2]),
        .I1(sel0[1]),
        .I2(sel0[4]),
        .I3(sel0[5]),
        .O(\HTIMER[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h3AAAAAAA)) 
    \HTIMER[10]_i_1 
       (.I0(\HTIMER[10]_i_2_n_0 ),
        .I1(sel0[10]),
        .I2(sel0[8]),
        .I3(sel0[9]),
        .I4(\HTIMER[10]_i_3_n_0 ),
        .O(HTIMER[10]));
  LUT6 #(
    .INIT(64'hAAAAAAA8AAAAAAAA)) 
    \HTIMER[10]_i_2 
       (.I0(sel0[10]),
        .I1(sel0[8]),
        .I2(sel0[6]),
        .I3(sel0[9]),
        .I4(sel0[7]),
        .I5(\HTIMER[10]_i_4_n_0 ),
        .O(\HTIMER[10]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \HTIMER[10]_i_3 
       (.I0(\HTIMER[9]_i_2_n_0 ),
        .I1(sel0[6]),
        .I2(sel0[7]),
        .O(\HTIMER[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \HTIMER[10]_i_4 
       (.I0(sel0[5]),
        .I1(sel0[3]),
        .I2(sel0[4]),
        .I3(sel0[2]),
        .I4(sel0[1]),
        .I5(sel0[0]),
        .O(\HTIMER[10]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \HTIMER[1]_i_1 
       (.I0(sel0[0]),
        .I1(sel0[1]),
        .O(HTIMER[1]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \HTIMER[2]_i_1 
       (.I0(sel0[2]),
        .I1(sel0[1]),
        .I2(sel0[0]),
        .O(\HTIMER[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \HTIMER[3]_i_1 
       (.I0(sel0[3]),
        .I1(sel0[1]),
        .I2(sel0[0]),
        .I3(sel0[2]),
        .O(HTIMER[3]));
  LUT6 #(
    .INIT(64'h1555555540000000)) 
    \HTIMER[4]_i_1 
       (.I0(\HTIMER[4]_i_2_n_0 ),
        .I1(sel0[2]),
        .I2(sel0[0]),
        .I3(sel0[1]),
        .I4(sel0[3]),
        .I5(sel0[4]),
        .O(HTIMER[4]));
  LUT6 #(
    .INIT(64'h0000000000000200)) 
    \HTIMER[4]_i_2 
       (.I0(\HTIMER[10]_i_4_n_0 ),
        .I1(sel0[8]),
        .I2(sel0[7]),
        .I3(sel0[10]),
        .I4(sel0[9]),
        .I5(sel0[6]),
        .O(\HTIMER[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \HTIMER[5]_i_1 
       (.I0(sel0[5]),
        .I1(sel0[4]),
        .I2(sel0[3]),
        .I3(sel0[1]),
        .I4(sel0[0]),
        .I5(sel0[2]),
        .O(\HTIMER[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \HTIMER[6]_i_1 
       (.I0(sel0[6]),
        .I1(\HTIMER[9]_i_2_n_0 ),
        .O(\HTIMER[6]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h9A)) 
    \HTIMER[7]_i_1 
       (.I0(sel0[7]),
        .I1(\HTIMER[9]_i_2_n_0 ),
        .I2(sel0[6]),
        .O(HTIMER[7]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \HTIMER[8]_i_1 
       (.I0(sel0[8]),
        .I1(sel0[7]),
        .I2(sel0[6]),
        .I3(\HTIMER[9]_i_2_n_0 ),
        .O(HTIMER[8]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h9AAAAAAA)) 
    \HTIMER[9]_i_1 
       (.I0(sel0[9]),
        .I1(\HTIMER[9]_i_2_n_0 ),
        .I2(sel0[6]),
        .I3(sel0[7]),
        .I4(sel0[8]),
        .O(HTIMER[9]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \HTIMER[9]_i_2 
       (.I0(sel0[4]),
        .I1(sel0[3]),
        .I2(sel0[1]),
        .I3(sel0[0]),
        .I4(sel0[2]),
        .I5(sel0[5]),
        .O(\HTIMER[9]_i_2_n_0 ));
  FDRE \HTIMER_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HTIMER[0]),
        .Q(sel0[0]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HTIMER[10]),
        .Q(sel0[10]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HTIMER[1]),
        .Q(sel0[1]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\HTIMER[2]_i_1_n_0 ),
        .Q(sel0[2]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HTIMER[3]),
        .Q(sel0[3]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HTIMER[4]),
        .Q(sel0[4]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\HTIMER[5]_i_1_n_0 ),
        .Q(sel0[5]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\HTIMER[6]_i_1_n_0 ),
        .Q(sel0[6]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HTIMER[7]),
        .Q(sel0[7]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HTIMER[8]),
        .Q(sel0[8]),
        .R(INTERNAL_RST_reg));
  FDRE \HTIMER_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(HTIMER[9]),
        .Q(sel0[9]),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'h00000000AAAEAAAA)) 
    INTHSYNCH_i_1
       (.I0(HSYNCH_DEL_reg),
        .I1(HBLANK_i_2_n_0),
        .I2(sel0[7]),
        .I3(sel0[8]),
        .I4(sel0[6]),
        .I5(VTIMER_EN_i_1_n_0),
        .O(INTHSYNCH_i_1_n_0));
  FDRE INTHSYNCH_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(INTHSYNCH_i_1_n_0),
        .Q(HSYNCH_DEL_reg),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000EEEE0EEE)) 
    INTVSYNCH_i_1
       (.I0(VSYNCH_DEL_reg),
        .I1(INTVSYNCH2_out),
        .I2(\VTIMER[2]_i_2_n_0 ),
        .I3(VTIMER_EN),
        .I4(VTIMER[0]),
        .I5(INTERNAL_RST_reg),
        .O(INTVSYNCH_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    INTVSYNCH_i_2
       (.I0(VBLANK_i_2_n_0),
        .I1(VTIMER[0]),
        .I2(INTVSYNCH_i_3_n_0),
        .I3(VTIMER[3]),
        .I4(VTIMER[5]),
        .I5(VTIMER[4]),
        .O(INTVSYNCH2_out));
  LUT2 #(
    .INIT(4'h7)) 
    INTVSYNCH_i_3
       (.I0(VTIMER[1]),
        .I1(VTIMER[2]),
        .O(INTVSYNCH_i_3_n_0));
  FDRE INTVSYNCH_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(INTVSYNCH_i_1_n_0),
        .Q(VSYNCH_DEL_reg),
        .R(1'b0));
  CARRY4 MEMORY_reg_0_i_1
       (.CI(MEMORY_reg_0_i_2_n_0),
        .CO(NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED[3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(ADDRBWRADDR[12:9]),
        .S(ROW_ADDRESS[12:9]));
  LUT2 #(
    .INIT(4'h6)) 
    MEMORY_reg_0_i_11
       (.I0(ROW_ADDRESS[6]),
        .I1(\COL_ADDRESS_reg_n_0_[6] ),
        .O(MEMORY_reg_0_i_11_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    MEMORY_reg_0_i_12
       (.I0(ROW_ADDRESS[5]),
        .I1(\COL_ADDRESS_reg_n_0_[5] ),
        .O(MEMORY_reg_0_i_12_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    MEMORY_reg_0_i_13
       (.I0(ROW_ADDRESS[4]),
        .I1(\COL_ADDRESS_reg_n_0_[4] ),
        .O(MEMORY_reg_0_i_13_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    MEMORY_reg_0_i_14
       (.I0(ROW_ADDRESS[3]),
        .I1(\COL_ADDRESS_reg_n_0_[3] ),
        .O(MEMORY_reg_0_i_14_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    MEMORY_reg_0_i_15
       (.I0(ROW_ADDRESS[2]),
        .I1(\COL_ADDRESS_reg_n_0_[2] ),
        .O(MEMORY_reg_0_i_15_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    MEMORY_reg_0_i_16
       (.I0(ROW_ADDRESS[1]),
        .I1(\COL_ADDRESS_reg_n_0_[1] ),
        .O(MEMORY_reg_0_i_16_n_0));
  CARRY4 MEMORY_reg_0_i_2
       (.CI(MEMORY_reg_0_i_3_n_0),
        .CO({MEMORY_reg_0_i_2_n_0,NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
        .O(ADDRBWRADDR[8:5]),
        .S({ROW_ADDRESS[8:7],MEMORY_reg_0_i_11_n_0,MEMORY_reg_0_i_12_n_0}));
  CARRY4 MEMORY_reg_0_i_3
       (.CI(1'b0),
        .CO({MEMORY_reg_0_i_3_n_0,NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(ROW_ADDRESS[4:1]),
        .O({ADDRBWRADDR[4:2],NLW_MEMORY_reg_0_i_3_O_UNCONNECTED[0]}),
        .S({MEMORY_reg_0_i_13_n_0,MEMORY_reg_0_i_14_n_0,MEMORY_reg_0_i_15_n_0,MEMORY_reg_0_i_16_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    MEMORY_reg_0_i_4
       (.I0(ROW_ADDRESS[1]),
        .I1(\COL_ADDRESS_reg_n_0_[1] ),
        .O(ADDRBWRADDR[1]));
  LUT3 #(
    .INIT(8'hE1)) 
    \PIX_COL_ADDRESS[0]_i_1 
       (.I0(VBLANK_reg_n_0),
        .I1(HBLANK_reg_n_0),
        .I2(\PIXCOL_DEL_reg[0] ),
        .O(\PIX_COL_ADDRESS[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'hFD02)) 
    \PIX_COL_ADDRESS[1]_i_1 
       (.I0(\PIXCOL_DEL_reg[0] ),
        .I1(HBLANK_reg_n_0),
        .I2(VBLANK_reg_n_0),
        .I3(\PIXCOL_DEL_reg[1] ),
        .O(\PIX_COL_ADDRESS[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT5 #(
    .INIT(32'hFFF70008)) 
    \PIX_COL_ADDRESS[2]_i_1 
       (.I0(\PIXCOL_DEL_reg[0] ),
        .I1(\PIXCOL_DEL_reg[1] ),
        .I2(HBLANK_reg_n_0),
        .I3(VBLANK_reg_n_0),
        .I4(\PIXCOL_DEL_reg[2] ),
        .O(\PIX_COL_ADDRESS[2]_i_1_n_0 ));
  FDRE \PIX_COL_ADDRESS_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\PIX_COL_ADDRESS[0]_i_1_n_0 ),
        .Q(\PIXCOL_DEL_reg[0] ),
        .R(INTERNAL_RST_reg));
  FDRE \PIX_COL_ADDRESS_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\PIX_COL_ADDRESS[1]_i_1_n_0 ),
        .Q(\PIXCOL_DEL_reg[1] ),
        .R(INTERNAL_RST_reg));
  FDRE \PIX_COL_ADDRESS_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\PIX_COL_ADDRESS[2]_i_1_n_0 ),
        .Q(\PIXCOL_DEL_reg[2] ),
        .R(INTERNAL_RST_reg));
  LUT2 #(
    .INIT(4'h6)) 
    \PIX_ROW_ADDRESS[0]_i_1 
       (.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
        .I1(\PIXROW_DEL_reg[0] ),
        .O(\PIX_ROW_ADDRESS[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \PIX_ROW_ADDRESS[1]_i_1 
       (.I0(\PIXROW_DEL_reg[0] ),
        .I1(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
        .I2(\PIXROW_DEL_reg[1] ),
        .O(\PIX_ROW_ADDRESS[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \PIX_ROW_ADDRESS[2]_i_1 
       (.I0(\PIXROW_DEL_reg[0] ),
        .I1(\PIXROW_DEL_reg[1] ),
        .I2(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
        .I3(D),
        .O(\PIX_ROW_ADDRESS[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \PIX_ROW_ADDRESS[2]_i_2 
       (.I0(VBLANK_reg_n_0),
        .I1(HBLANK_reg_n_0),
        .I2(\PIXCOL_DEL_reg[2] ),
        .I3(\PIXCOL_DEL_reg[1] ),
        .I4(\PIXCOL_DEL_reg[0] ),
        .I5(\PIX_ROW_ADDRESS[2]_i_3_n_0 ),
        .O(\PIX_ROW_ADDRESS[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF7)) 
    \PIX_ROW_ADDRESS[2]_i_3 
       (.I0(\COL_ADDRESS_reg_n_0_[5] ),
        .I1(\COL_ADDRESS_reg_n_0_[6] ),
        .I2(\COL_ADDRESS_reg_n_0_[2] ),
        .I3(\COL_ADDRESS_reg_n_0_[3] ),
        .I4(\COL_ADDRESS_reg_n_0_[4] ),
        .I5(\COL_ADDRESS[6]_i_3_n_0 ),
        .O(\PIX_ROW_ADDRESS[2]_i_3_n_0 ));
  FDRE \PIX_ROW_ADDRESS_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\PIX_ROW_ADDRESS[0]_i_1_n_0 ),
        .Q(\PIXROW_DEL_reg[0] ),
        .R(INTERNAL_RST_reg));
  FDRE \PIX_ROW_ADDRESS_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\PIX_ROW_ADDRESS[1]_i_1_n_0 ),
        .Q(\PIXROW_DEL_reg[1] ),
        .R(INTERNAL_RST_reg));
  FDRE \PIX_ROW_ADDRESS_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\PIX_ROW_ADDRESS[2]_i_1_n_0 ),
        .Q(D),
        .R(INTERNAL_RST_reg));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[10]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[12]_i_5_n_6 ),
        .O(ROW_ADDRESS_0[10]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[11]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[12]_i_5_n_5 ),
        .O(ROW_ADDRESS_0[11]));
  LUT4 #(
    .INIT(16'h8000)) 
    \ROW_ADDRESS[12]_i_1 
       (.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
        .I1(D),
        .I2(\PIXROW_DEL_reg[0] ),
        .I3(\PIXROW_DEL_reg[1] ),
        .O(\ROW_ADDRESS[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[12]_i_2 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[12]_i_5_n_4 ),
        .O(ROW_ADDRESS_0[12]));
  LUT6 #(
    .INIT(64'h0040000000000000)) 
    \ROW_ADDRESS[12]_i_3 
       (.I0(ROW_ADDRESS[9]),
        .I1(ROW_ADDRESS[10]),
        .I2(ROW_ADDRESS[7]),
        .I3(ROW_ADDRESS[8]),
        .I4(ROW_ADDRESS[11]),
        .I5(ROW_ADDRESS[12]),
        .O(\ROW_ADDRESS[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \ROW_ADDRESS[12]_i_4 
       (.I0(ROW_ADDRESS[6]),
        .I1(ROW_ADDRESS[5]),
        .I2(ROW_ADDRESS[3]),
        .I3(ROW_ADDRESS[4]),
        .I4(ROW_ADDRESS[1]),
        .I5(ROW_ADDRESS[2]),
        .O(\ROW_ADDRESS[12]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[1]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[4]_i_2_n_7 ),
        .O(ROW_ADDRESS_0[1]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[2]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[4]_i_2_n_6 ),
        .O(ROW_ADDRESS_0[2]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[3]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[4]_i_2_n_5 ),
        .O(ROW_ADDRESS_0[3]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[4]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[4]_i_2_n_4 ),
        .O(ROW_ADDRESS_0[4]));
  LUT1 #(
    .INIT(2'h1)) 
    \ROW_ADDRESS[4]_i_5 
       (.I0(ROW_ADDRESS[2]),
        .O(\ROW_ADDRESS[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[5]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[8]_i_2_n_7 ),
        .O(ROW_ADDRESS_0[5]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[6]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[8]_i_2_n_6 ),
        .O(ROW_ADDRESS_0[6]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[7]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[8]_i_2_n_5 ),
        .O(ROW_ADDRESS_0[7]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[8]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[8]_i_2_n_4 ),
        .O(ROW_ADDRESS_0[8]));
  LUT1 #(
    .INIT(2'h1)) 
    \ROW_ADDRESS[8]_i_5 
       (.I0(ROW_ADDRESS[6]),
        .O(\ROW_ADDRESS[8]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \ROW_ADDRESS[8]_i_6 
       (.I0(ROW_ADDRESS[5]),
        .O(\ROW_ADDRESS[8]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \ROW_ADDRESS[9]_i_1 
       (.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
        .I1(\ROW_ADDRESS[12]_i_4_n_0 ),
        .I2(\ROW_ADDRESS_reg[12]_i_5_n_7 ),
        .O(ROW_ADDRESS_0[9]));
  FDRE \ROW_ADDRESS_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[10]),
        .Q(ROW_ADDRESS[10]),
        .R(INTERNAL_RST_reg));
  FDRE \ROW_ADDRESS_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[11]),
        .Q(ROW_ADDRESS[11]),
        .R(INTERNAL_RST_reg));
  FDRE \ROW_ADDRESS_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[12]),
        .Q(ROW_ADDRESS[12]),
        .R(INTERNAL_RST_reg));
  CARRY4 \ROW_ADDRESS_reg[12]_i_5 
       (.CI(\ROW_ADDRESS_reg[8]_i_2_n_0 ),
        .CO(\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\ROW_ADDRESS_reg[12]_i_5_n_4 ,\ROW_ADDRESS_reg[12]_i_5_n_5 ,\ROW_ADDRESS_reg[12]_i_5_n_6 ,\ROW_ADDRESS_reg[12]_i_5_n_7 }),
        .S(ROW_ADDRESS[12:9]));
  FDRE \ROW_ADDRESS_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[1]),
        .Q(ROW_ADDRESS[1]),
        .R(INTERNAL_RST_reg));
  FDRE \ROW_ADDRESS_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[2]),
        .Q(ROW_ADDRESS[2]),
        .R(INTERNAL_RST_reg));
  FDRE \ROW_ADDRESS_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[3]),
        .Q(ROW_ADDRESS[3]),
        .R(INTERNAL_RST_reg));
  FDRE \ROW_ADDRESS_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[4]),
        .Q(ROW_ADDRESS[4]),
        .R(INTERNAL_RST_reg));
  CARRY4 \ROW_ADDRESS_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\ROW_ADDRESS_reg[4]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,ROW_ADDRESS[2],1'b0}),
        .O({\ROW_ADDRESS_reg[4]_i_2_n_4 ,\ROW_ADDRESS_reg[4]_i_2_n_5 ,\ROW_ADDRESS_reg[4]_i_2_n_6 ,\ROW_ADDRESS_reg[4]_i_2_n_7 }),
        .S({ROW_ADDRESS[4:3],\ROW_ADDRESS[4]_i_5_n_0 ,ROW_ADDRESS[1]}));
  FDRE \ROW_ADDRESS_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[5]),
        .Q(ROW_ADDRESS[5]),
        .R(INTERNAL_RST_reg));
  FDRE \ROW_ADDRESS_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[6]),
        .Q(ROW_ADDRESS[6]),
        .R(INTERNAL_RST_reg));
  FDRE \ROW_ADDRESS_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[7]),
        .Q(ROW_ADDRESS[7]),
        .R(INTERNAL_RST_reg));
  FDRE \ROW_ADDRESS_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[8]),
        .Q(ROW_ADDRESS[8]),
        .R(INTERNAL_RST_reg));
  CARRY4 \ROW_ADDRESS_reg[8]_i_2 
       (.CI(\ROW_ADDRESS_reg[4]_i_2_n_0 ),
        .CO({\ROW_ADDRESS_reg[8]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
        .O({\ROW_ADDRESS_reg[8]_i_2_n_4 ,\ROW_ADDRESS_reg[8]_i_2_n_5 ,\ROW_ADDRESS_reg[8]_i_2_n_6 ,\ROW_ADDRESS_reg[8]_i_2_n_7 }),
        .S({ROW_ADDRESS[8:7],\ROW_ADDRESS[8]_i_5_n_0 ,\ROW_ADDRESS[8]_i_6_n_0 }));
  FDRE \ROW_ADDRESS_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\ROW_ADDRESS[12]_i_1_n_0 ),
        .D(ROW_ADDRESS_0[9]),
        .Q(ROW_ADDRESS[9]),
        .R(INTERNAL_RST_reg));
  LUT4 #(
    .INIT(16'hFFD0)) 
    VBLANK_i_1
       (.I0(VBLANK_i_2_n_0),
        .I1(VBLANK_i_3_n_0),
        .I2(VBLANK_reg_n_0),
        .I3(VBLANK_i_4_n_0),
        .O(VBLANK_i_1_n_0));
  LUT5 #(
    .INIT(32'h00000004)) 
    VBLANK_i_2
       (.I0(VTIMER[7]),
        .I1(VTIMER_EN),
        .I2(VTIMER[8]),
        .I3(VTIMER[9]),
        .I4(VTIMER[6]),
        .O(VBLANK_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFBFFFFFFFFFF)) 
    VBLANK_i_3
       (.I0(VTIMER[2]),
        .I1(VTIMER[0]),
        .I2(VTIMER[1]),
        .I3(VTIMER[5]),
        .I4(VTIMER[4]),
        .I5(VTIMER[3]),
        .O(VBLANK_i_3_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAABA)) 
    VBLANK_i_4
       (.I0(INTERNAL_RST_reg),
        .I1(VBLANK_i_5_n_0),
        .I2(VTIMER_EN),
        .I3(VBLANK_i_6_n_0),
        .I4(VTIMER[6]),
        .I5(VBLANK_i_7_n_0),
        .O(VBLANK_i_4_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    VBLANK_i_5
       (.I0(VTIMER[3]),
        .I1(VTIMER[5]),
        .I2(VTIMER[4]),
        .O(VBLANK_i_5_n_0));
  LUT3 #(
    .INIT(8'hFB)) 
    VBLANK_i_6
       (.I0(VTIMER[1]),
        .I1(VTIMER[0]),
        .I2(VTIMER[2]),
        .O(VBLANK_i_6_n_0));
  LUT3 #(
    .INIT(8'hDF)) 
    VBLANK_i_7
       (.I0(VTIMER[9]),
        .I1(VTIMER[8]),
        .I2(VTIMER[7]),
        .O(VBLANK_i_7_n_0));
  FDRE VBLANK_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(VBLANK_i_1_n_0),
        .Q(VBLANK_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \VTIMER[0]_i_1 
       (.I0(VTIMER[0]),
        .I1(\VTIMER[2]_i_2_n_0 ),
        .O(\VTIMER[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \VTIMER[1]_i_1 
       (.I0(VTIMER[0]),
        .I1(VTIMER[1]),
        .I2(\VTIMER[2]_i_2_n_0 ),
        .O(VTIMER_1[1]));
  LUT4 #(
    .INIT(16'h0078)) 
    \VTIMER[2]_i_1 
       (.I0(VTIMER[1]),
        .I1(VTIMER[0]),
        .I2(VTIMER[2]),
        .I3(\VTIMER[2]_i_2_n_0 ),
        .O(VTIMER_1[2]));
  LUT6 #(
    .INIT(64'h0222000000000000)) 
    \VTIMER[2]_i_2 
       (.I0(\VTIMER[2]_i_3_n_0 ),
        .I1(VTIMER[5]),
        .I2(VTIMER[3]),
        .I3(VTIMER[4]),
        .I4(VTIMER[1]),
        .I5(VTIMER[2]),
        .O(\VTIMER[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    \VTIMER[2]_i_3 
       (.I0(VTIMER[8]),
        .I1(VTIMER[9]),
        .I2(VTIMER[4]),
        .I3(VTIMER[5]),
        .I4(VTIMER[7]),
        .I5(VTIMER[6]),
        .O(\VTIMER[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6AAA)) 
    \VTIMER[3]_i_1 
       (.I0(VTIMER[3]),
        .I1(VTIMER[2]),
        .I2(VTIMER[1]),
        .I3(VTIMER[0]),
        .O(VTIMER_1[3]));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \VTIMER[4]_i_1 
       (.I0(VTIMER[0]),
        .I1(VTIMER[1]),
        .I2(VTIMER[2]),
        .I3(VTIMER[3]),
        .I4(VTIMER[4]),
        .I5(\VTIMER[9]_i_3_n_0 ),
        .O(VTIMER_1[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \VTIMER[5]_i_1 
       (.I0(VTIMER[5]),
        .I1(VTIMER[4]),
        .I2(VTIMER[0]),
        .I3(VTIMER[1]),
        .I4(VTIMER[2]),
        .I5(VTIMER[3]),
        .O(\VTIMER[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \VTIMER[6]_i_1 
       (.I0(VTIMER[6]),
        .I1(\VTIMER[9]_i_2_n_0 ),
        .O(VTIMER_1[6]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'h1540)) 
    \VTIMER[7]_i_1 
       (.I0(\VTIMER[9]_i_3_n_0 ),
        .I1(\VTIMER[9]_i_2_n_0 ),
        .I2(VTIMER[6]),
        .I3(VTIMER[7]),
        .O(VTIMER_1[7]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \VTIMER[8]_i_1 
       (.I0(VTIMER[8]),
        .I1(VTIMER[7]),
        .I2(VTIMER[6]),
        .I3(\VTIMER[9]_i_2_n_0 ),
        .O(VTIMER_1[8]));
  LUT6 #(
    .INIT(64'h000000006AAAAAAA)) 
    \VTIMER[9]_i_1 
       (.I0(VTIMER[9]),
        .I1(\VTIMER[9]_i_2_n_0 ),
        .I2(VTIMER[6]),
        .I3(VTIMER[7]),
        .I4(VTIMER[8]),
        .I5(\VTIMER[9]_i_3_n_0 ),
        .O(VTIMER_1[9]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \VTIMER[9]_i_2 
       (.I0(VTIMER[5]),
        .I1(VTIMER[4]),
        .I2(VTIMER[0]),
        .I3(VTIMER[1]),
        .I4(VTIMER[2]),
        .I5(VTIMER[3]),
        .O(\VTIMER[9]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \VTIMER[9]_i_3 
       (.I0(VTIMER[7]),
        .I1(\VTIMER[9]_i_4_n_0 ),
        .I2(VTIMER[9]),
        .I3(VTIMER[8]),
        .I4(\VTIMER[9]_i_5_n_0 ),
        .O(\VTIMER[9]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hF8FF)) 
    \VTIMER[9]_i_4 
       (.I0(VTIMER[6]),
        .I1(VTIMER[7]),
        .I2(VTIMER[5]),
        .I3(VTIMER[4]),
        .O(\VTIMER[9]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF7F7F7)) 
    \VTIMER[9]_i_5 
       (.I0(VTIMER[1]),
        .I1(VTIMER[2]),
        .I2(VTIMER[0]),
        .I3(VTIMER[4]),
        .I4(VTIMER[3]),
        .I5(VTIMER[5]),
        .O(\VTIMER[9]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    VTIMER_EN_i_1
       (.I0(INTERNAL_RST_reg),
        .I1(\HTIMER[4]_i_2_n_0 ),
        .O(VTIMER_EN_i_1_n_0));
  FDRE VTIMER_EN_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(VTIMER_EN_i_1_n_0),
        .Q(VTIMER_EN),
        .R(1'b0));
  FDRE \VTIMER_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(\VTIMER[0]_i_1_n_0 ),
        .Q(VTIMER[0]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(VTIMER_1[1]),
        .Q(VTIMER[1]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(VTIMER_1[2]),
        .Q(VTIMER[2]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(VTIMER_1[3]),
        .Q(VTIMER[3]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(VTIMER_1[4]),
        .Q(VTIMER[4]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(\VTIMER[5]_i_1_n_0 ),
        .Q(VTIMER[5]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(VTIMER_1[6]),
        .Q(VTIMER[6]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(VTIMER_1[7]),
        .Q(VTIMER[7]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(VTIMER_1[8]),
        .Q(VTIMER[8]),
        .R(INTERNAL_RST_reg));
  FDRE \VTIMER_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(VTIMER_EN),
        .D(VTIMER_1[9]),
        .Q(VTIMER[9]),
        .R(INTERNAL_RST_reg));
endmodule

module main_0
   (IN1_STB,
    OUT1_ACK,
    output_rs232_out,
    INTERNAL_RST_reg,
    OUT1,
    IN1_ACK,
    ETH_CLK_OBUF,
    OUT1_STB);
  output IN1_STB;
  output OUT1_ACK;
  output [7:0]output_rs232_out;
  input INTERNAL_RST_reg;
  input [7:0]OUT1;
  input IN1_ACK;
  input ETH_CLK_OBUF;
  input OUT1_STB;

  wire ETH_CLK_OBUF;
  wire IN1_ACK;
  wire IN1_STB;
  wire INTERNAL_RST_reg;
  wire [7:0]OUT1;
  wire OUT1_ACK;
  wire OUT1_STB;
  wire [3:0]address_a;
  wire [3:0]address_a_2;
  wire [3:0]address_b_2;
  wire [3:0]address_z;
  wire [3:0]address_z_2;
  wire [3:0]address_z_3;
  wire \address_z_3[3]_i_1_n_0 ;
  wire data10;
  wire data12;
  wire [16:1]data2;
  wire data4;
  wire [31:0]data5;
  wire data6;
  wire [31:20]data7;
  wire instruction0;
  wire [31:0]load_data;
  wire memory_reg_0_i_1_n_0;
  wire memory_reg_0_i_2_n_0;
  wire memory_reg_1_ENARDEN_cooolgate_en_sig_1;
  wire memory_reg_2_ENARDEN_cooolgate_en_sig_2;
  wire memory_reg_3_ENARDEN_cooolgate_en_sig_3;
  wire memory_reg_4_ENARDEN_cooolgate_en_sig_4;
  wire memory_reg_5_ENARDEN_cooolgate_en_sig_5;
  wire memory_reg_6_ENARDEN_cooolgate_en_sig_6;
  wire memory_reg_7_ENARDEN_cooolgate_en_sig_7;
  wire [4:0]opcode;
  wire [4:0]opcode_2;
  wire opcode_20;
  wire operand_a1;
  wire operand_b1;
  wire out0;
  wire [7:0]output_rs232_out;
  wire \program_counter[0]_i_2_n_0 ;
  wire \program_counter[0]_i_3_n_0 ;
  wire \program_counter[0]_i_4_n_0 ;
  wire \program_counter[10]_i_2_n_0 ;
  wire \program_counter[10]_i_3_n_0 ;
  wire \program_counter[10]_i_4_n_0 ;
  wire \program_counter[11]_i_2_n_0 ;
  wire \program_counter[11]_i_3_n_0 ;
  wire \program_counter[11]_i_4_n_0 ;
  wire \program_counter[12]_i_3_n_0 ;
  wire \program_counter[12]_i_4_n_0 ;
  wire \program_counter[12]_i_5_n_0 ;
  wire \program_counter[13]_i_2_n_0 ;
  wire \program_counter[13]_i_3_n_0 ;
  wire \program_counter[13]_i_4_n_0 ;
  wire \program_counter[14]_i_2_n_0 ;
  wire \program_counter[14]_i_3_n_0 ;
  wire \program_counter[14]_i_4_n_0 ;
  wire \program_counter[15]_i_13_n_0 ;
  wire \program_counter[15]_i_14_n_0 ;
  wire \program_counter[15]_i_15_n_0 ;
  wire \program_counter[15]_i_16_n_0 ;
  wire \program_counter[15]_i_17_n_0 ;
  wire \program_counter[15]_i_18_n_0 ;
  wire \program_counter[15]_i_19_n_0 ;
  wire \program_counter[15]_i_20_n_0 ;
  wire \program_counter[15]_i_21_n_0 ;
  wire \program_counter[15]_i_3_n_0 ;
  wire \program_counter[15]_i_5_n_0 ;
  wire \program_counter[15]_i_6_n_0 ;
  wire \program_counter[15]_i_7_n_0 ;
  wire \program_counter[15]_i_8_n_0 ;
  wire \program_counter[15]_i_9_n_0 ;
  wire \program_counter[1]_i_2_n_0 ;
  wire \program_counter[1]_i_3_n_0 ;
  wire \program_counter[1]_i_4_n_0 ;
  wire \program_counter[2]_i_2_n_0 ;
  wire \program_counter[2]_i_3_n_0 ;
  wire \program_counter[2]_i_4_n_0 ;
  wire \program_counter[3]_i_2_n_0 ;
  wire \program_counter[3]_i_3_n_0 ;
  wire \program_counter[3]_i_4_n_0 ;
  wire \program_counter[4]_i_3_n_0 ;
  wire \program_counter[4]_i_4_n_0 ;
  wire \program_counter[4]_i_5_n_0 ;
  wire \program_counter[5]_i_2_n_0 ;
  wire \program_counter[5]_i_3_n_0 ;
  wire \program_counter[5]_i_4_n_0 ;
  wire \program_counter[6]_i_2_n_0 ;
  wire \program_counter[6]_i_3_n_0 ;
  wire \program_counter[6]_i_4_n_0 ;
  wire \program_counter[7]_i_2_n_0 ;
  wire \program_counter[7]_i_3_n_0 ;
  wire \program_counter[7]_i_4_n_0 ;
  wire \program_counter[8]_i_3_n_0 ;
  wire \program_counter[8]_i_4_n_0 ;
  wire \program_counter[8]_i_5_n_0 ;
  wire \program_counter[9]_i_2_n_0 ;
  wire \program_counter[9]_i_3_n_0 ;
  wire \program_counter[9]_i_4_n_0 ;
  wire [15:0]program_counter_1;
  wire [15:0]program_counter_2;
  wire \program_counter_reg[12]_i_2_n_0 ;
  wire \program_counter_reg[12]_i_2_n_4 ;
  wire \program_counter_reg[12]_i_2_n_5 ;
  wire \program_counter_reg[12]_i_2_n_6 ;
  wire \program_counter_reg[12]_i_2_n_7 ;
  wire \program_counter_reg[15]_i_4_n_5 ;
  wire \program_counter_reg[15]_i_4_n_6 ;
  wire \program_counter_reg[15]_i_4_n_7 ;
  wire \program_counter_reg[4]_i_2_n_0 ;
  wire \program_counter_reg[4]_i_2_n_4 ;
  wire \program_counter_reg[4]_i_2_n_5 ;
  wire \program_counter_reg[4]_i_2_n_6 ;
  wire \program_counter_reg[4]_i_2_n_7 ;
  wire \program_counter_reg[8]_i_2_n_0 ;
  wire \program_counter_reg[8]_i_2_n_4 ;
  wire \program_counter_reg[8]_i_2_n_5 ;
  wire \program_counter_reg[8]_i_2_n_6 ;
  wire \program_counter_reg[8]_i_2_n_7 ;
  wire \program_counter_reg_n_0_[0] ;
  wire \program_counter_reg_n_0_[10] ;
  wire \program_counter_reg_n_0_[11] ;
  wire \program_counter_reg_n_0_[12] ;
  wire \program_counter_reg_n_0_[13] ;
  wire \program_counter_reg_n_0_[14] ;
  wire \program_counter_reg_n_0_[15] ;
  wire \program_counter_reg_n_0_[1] ;
  wire \program_counter_reg_n_0_[2] ;
  wire \program_counter_reg_n_0_[3] ;
  wire \program_counter_reg_n_0_[4] ;
  wire \program_counter_reg_n_0_[5] ;
  wire \program_counter_reg_n_0_[6] ;
  wire \program_counter_reg_n_0_[7] ;
  wire \program_counter_reg_n_0_[8] ;
  wire \program_counter_reg_n_0_[9] ;
  wire program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11;
  wire program_counter_reg_rep_0_i_10_n_0;
  wire program_counter_reg_rep_0_i_11_n_0;
  wire program_counter_reg_rep_0_i_12_n_0;
  wire program_counter_reg_rep_0_i_13_n_0;
  wire program_counter_reg_rep_0_i_14_n_0;
  wire program_counter_reg_rep_0_i_15_n_0;
  wire program_counter_reg_rep_0_i_16_n_0;
  wire program_counter_reg_rep_0_i_17_n_0;
  wire program_counter_reg_rep_0_i_18_n_0;
  wire program_counter_reg_rep_0_i_19_n_0;
  wire program_counter_reg_rep_0_i_1_n_0;
  wire program_counter_reg_rep_0_i_20_n_0;
  wire program_counter_reg_rep_0_i_21_n_0;
  wire program_counter_reg_rep_0_i_22_n_0;
  wire program_counter_reg_rep_0_i_23_n_0;
  wire program_counter_reg_rep_0_i_24_n_0;
  wire program_counter_reg_rep_0_i_25_n_0;
  wire program_counter_reg_rep_0_i_26_n_0;
  wire program_counter_reg_rep_0_i_27_n_0;
  wire program_counter_reg_rep_0_i_2_n_0;
  wire program_counter_reg_rep_0_i_3_n_0;
  wire program_counter_reg_rep_0_i_4_n_0;
  wire program_counter_reg_rep_0_i_5_n_0;
  wire program_counter_reg_rep_0_i_6_n_0;
  wire program_counter_reg_rep_0_i_7_n_0;
  wire program_counter_reg_rep_0_i_8_n_0;
  wire program_counter_reg_rep_0_i_9_n_0;
  wire program_counter_reg_rep_0_n_32;
  wire program_counter_reg_rep_0_n_33;
  wire program_counter_reg_rep_0_n_34;
  wire program_counter_reg_rep_0_n_35;
  wire program_counter_reg_rep_1_n_32;
  wire program_counter_reg_rep_1_n_33;
  wire program_counter_reg_rep_1_n_34;
  wire program_counter_reg_rep_1_n_35;
  wire program_counter_reg_rep_2_n_32;
  wire program_counter_reg_rep_2_n_33;
  wire program_counter_reg_rep_2_n_34;
  wire program_counter_reg_rep_2_n_35;
  wire program_counter_reg_rep_3_n_32;
  wire program_counter_reg_rep_3_n_33;
  wire program_counter_reg_rep_3_n_34;
  wire program_counter_reg_rep_3_n_35;
  wire [31:0]read_input;
  wire \read_input[0]_i_1_n_0 ;
  wire \read_input[10]_i_1_n_0 ;
  wire \read_input[11]_i_1_n_0 ;
  wire \read_input[12]_i_1_n_0 ;
  wire \read_input[13]_i_1_n_0 ;
  wire \read_input[14]_i_1_n_0 ;
  wire \read_input[15]_i_1_n_0 ;
  wire \read_input[16]_i_1_n_0 ;
  wire \read_input[17]_i_1_n_0 ;
  wire \read_input[18]_i_1_n_0 ;
  wire \read_input[19]_i_1_n_0 ;
  wire \read_input[1]_i_1_n_0 ;
  wire \read_input[20]_i_1_n_0 ;
  wire \read_input[21]_i_1_n_0 ;
  wire \read_input[22]_i_1_n_0 ;
  wire \read_input[23]_i_1_n_0 ;
  wire \read_input[24]_i_1_n_0 ;
  wire \read_input[25]_i_1_n_0 ;
  wire \read_input[26]_i_1_n_0 ;
  wire \read_input[27]_i_1_n_0 ;
  wire \read_input[28]_i_1_n_0 ;
  wire \read_input[29]_i_1_n_0 ;
  wire \read_input[2]_i_1_n_0 ;
  wire \read_input[30]_i_1_n_0 ;
  wire \read_input[31]_i_1_n_0 ;
  wire \read_input[31]_i_2_n_0 ;
  wire \read_input[31]_i_3_n_0 ;
  wire \read_input[31]_i_4_n_0 ;
  wire \read_input[31]_i_5_n_0 ;
  wire \read_input[3]_i_1_n_0 ;
  wire \read_input[4]_i_1_n_0 ;
  wire \read_input[5]_i_1_n_0 ;
  wire \read_input[6]_i_1_n_0 ;
  wire \read_input[7]_i_1_n_0 ;
  wire \read_input[8]_i_1_n_0 ;
  wire \read_input[9]_i_1_n_0 ;
  wire [31:0]register_a;
  wire [31:0]register_b;
  wire [31:0]result;
  wire \result[0]_i_100_n_0 ;
  wire \result[0]_i_101_n_0 ;
  wire \result[0]_i_102_n_0 ;
  wire \result[0]_i_103_n_0 ;
  wire \result[0]_i_104_n_0 ;
  wire \result[0]_i_105_n_0 ;
  wire \result[0]_i_106_n_0 ;
  wire \result[0]_i_107_n_0 ;
  wire \result[0]_i_108_n_0 ;
  wire \result[0]_i_109_n_0 ;
  wire \result[0]_i_110_n_0 ;
  wire \result[0]_i_111_n_0 ;
  wire \result[0]_i_112_n_0 ;
  wire \result[0]_i_113_n_0 ;
  wire \result[0]_i_114_n_0 ;
  wire \result[0]_i_115_n_0 ;
  wire \result[0]_i_116_n_0 ;
  wire \result[0]_i_117_n_0 ;
  wire \result[0]_i_118_n_0 ;
  wire \result[0]_i_119_n_0 ;
  wire \result[0]_i_11_n_0 ;
  wire \result[0]_i_120_n_0 ;
  wire \result[0]_i_15_n_0 ;
  wire \result[0]_i_16_n_0 ;
  wire \result[0]_i_17_n_0 ;
  wire \result[0]_i_18_n_0 ;
  wire \result[0]_i_19_n_0 ;
  wire \result[0]_i_1_n_0 ;
  wire \result[0]_i_20_n_0 ;
  wire \result[0]_i_21_n_0 ;
  wire \result[0]_i_22_n_0 ;
  wire \result[0]_i_24_n_0 ;
  wire \result[0]_i_25_n_0 ;
  wire \result[0]_i_26_n_0 ;
  wire \result[0]_i_27_n_0 ;
  wire \result[0]_i_28_n_0 ;
  wire \result[0]_i_2_n_0 ;
  wire \result[0]_i_30_n_0 ;
  wire \result[0]_i_31_n_0 ;
  wire \result[0]_i_32_n_0 ;
  wire \result[0]_i_34_n_0 ;
  wire \result[0]_i_35_n_0 ;
  wire \result[0]_i_36_n_0 ;
  wire \result[0]_i_37_n_0 ;
  wire \result[0]_i_39_n_0 ;
  wire \result[0]_i_3_n_0 ;
  wire \result[0]_i_40_n_0 ;
  wire \result[0]_i_41_n_0 ;
  wire \result[0]_i_42_n_0 ;
  wire \result[0]_i_43_n_0 ;
  wire \result[0]_i_44_n_0 ;
  wire \result[0]_i_45_n_0 ;
  wire \result[0]_i_46_n_0 ;
  wire \result[0]_i_47_n_0 ;
  wire \result[0]_i_48_n_0 ;
  wire \result[0]_i_49_n_0 ;
  wire \result[0]_i_4_n_0 ;
  wire \result[0]_i_50_n_0 ;
  wire \result[0]_i_51_n_0 ;
  wire \result[0]_i_53_n_0 ;
  wire \result[0]_i_54_n_0 ;
  wire \result[0]_i_55_n_0 ;
  wire \result[0]_i_56_n_0 ;
  wire \result[0]_i_58_n_0 ;
  wire \result[0]_i_59_n_0 ;
  wire \result[0]_i_5_n_0 ;
  wire \result[0]_i_60_n_0 ;
  wire \result[0]_i_61_n_0 ;
  wire \result[0]_i_62_n_0 ;
  wire \result[0]_i_63_n_0 ;
  wire \result[0]_i_65_n_0 ;
  wire \result[0]_i_66_n_0 ;
  wire \result[0]_i_67_n_0 ;
  wire \result[0]_i_68_n_0 ;
  wire \result[0]_i_6_n_0 ;
  wire \result[0]_i_70_n_0 ;
  wire \result[0]_i_71_n_0 ;
  wire \result[0]_i_72_n_0 ;
  wire \result[0]_i_73_n_0 ;
  wire \result[0]_i_74_n_0 ;
  wire \result[0]_i_75_n_0 ;
  wire \result[0]_i_76_n_0 ;
  wire \result[0]_i_77_n_0 ;
  wire \result[0]_i_78_n_0 ;
  wire \result[0]_i_79_n_0 ;
  wire \result[0]_i_80_n_0 ;
  wire \result[0]_i_81_n_0 ;
  wire \result[0]_i_83_n_0 ;
  wire \result[0]_i_84_n_0 ;
  wire \result[0]_i_85_n_0 ;
  wire \result[0]_i_86_n_0 ;
  wire \result[0]_i_87_n_0 ;
  wire \result[0]_i_88_n_0 ;
  wire \result[0]_i_89_n_0 ;
  wire \result[0]_i_8_n_0 ;
  wire \result[0]_i_90_n_0 ;
  wire \result[0]_i_91_n_0 ;
  wire \result[0]_i_92_n_0 ;
  wire \result[0]_i_93_n_0 ;
  wire \result[0]_i_94_n_0 ;
  wire \result[0]_i_96_n_0 ;
  wire \result[0]_i_97_n_0 ;
  wire \result[0]_i_98_n_0 ;
  wire \result[0]_i_99_n_0 ;
  wire \result[0]_i_9_n_0 ;
  wire \result[10]_i_1_n_0 ;
  wire \result[10]_i_2_n_0 ;
  wire \result[10]_i_3_n_0 ;
  wire \result[10]_i_4_n_0 ;
  wire \result[10]_i_5_n_0 ;
  wire \result[10]_i_6_n_0 ;
  wire \result[10]_i_7_n_0 ;
  wire \result[11]_i_10_n_0 ;
  wire \result[11]_i_11_n_0 ;
  wire \result[11]_i_12_n_0 ;
  wire \result[11]_i_1_n_0 ;
  wire \result[11]_i_2_n_0 ;
  wire \result[11]_i_3_n_0 ;
  wire \result[11]_i_4_n_0 ;
  wire \result[11]_i_5_n_0 ;
  wire \result[11]_i_6_n_0 ;
  wire \result[11]_i_7_n_0 ;
  wire \result[11]_i_9_n_0 ;
  wire \result[12]_i_1_n_0 ;
  wire \result[12]_i_2_n_0 ;
  wire \result[12]_i_3_n_0 ;
  wire \result[12]_i_4_n_0 ;
  wire \result[12]_i_5_n_0 ;
  wire \result[12]_i_6_n_0 ;
  wire \result[12]_i_7_n_0 ;
  wire \result[13]_i_1_n_0 ;
  wire \result[13]_i_2_n_0 ;
  wire \result[13]_i_3_n_0 ;
  wire \result[13]_i_4_n_0 ;
  wire \result[13]_i_5_n_0 ;
  wire \result[13]_i_6_n_0 ;
  wire \result[13]_i_7_n_0 ;
  wire \result[13]_i_8_n_0 ;
  wire \result[14]_i_1_n_0 ;
  wire \result[14]_i_2_n_0 ;
  wire \result[14]_i_3_n_0 ;
  wire \result[14]_i_4_n_0 ;
  wire \result[14]_i_5_n_0 ;
  wire \result[14]_i_6_n_0 ;
  wire \result[14]_i_7_n_0 ;
  wire \result[14]_i_8_n_0 ;
  wire \result[15]_i_12_n_0 ;
  wire \result[15]_i_13_n_0 ;
  wire \result[15]_i_14_n_0 ;
  wire \result[15]_i_15_n_0 ;
  wire \result[15]_i_17_n_0 ;
  wire \result[15]_i_18_n_0 ;
  wire \result[15]_i_19_n_0 ;
  wire \result[15]_i_1_n_0 ;
  wire \result[15]_i_20_n_0 ;
  wire \result[15]_i_21_n_0 ;
  wire \result[15]_i_22_n_0 ;
  wire \result[15]_i_23_n_0 ;
  wire \result[15]_i_24_n_0 ;
  wire \result[15]_i_25_n_0 ;
  wire \result[15]_i_26_n_0 ;
  wire \result[15]_i_27_n_0 ;
  wire \result[15]_i_28_n_0 ;
  wire \result[15]_i_29_n_0 ;
  wire \result[15]_i_2_n_0 ;
  wire \result[15]_i_30_n_0 ;
  wire \result[15]_i_31_n_0 ;
  wire \result[15]_i_32_n_0 ;
  wire \result[15]_i_3_n_0 ;
  wire \result[15]_i_4_n_0 ;
  wire \result[15]_i_5_n_0 ;
  wire \result[15]_i_6_n_0 ;
  wire \result[15]_i_9_n_0 ;
  wire \result[16]_i_1_n_0 ;
  wire \result[16]_i_2_n_0 ;
  wire \result[16]_i_3_n_0 ;
  wire \result[16]_i_4_n_0 ;
  wire \result[16]_i_5_n_0 ;
  wire \result[16]_i_6_n_0 ;
  wire \result[16]_i_8_n_0 ;
  wire \result[16]_i_9_n_0 ;
  wire \result[17]_i_1_n_0 ;
  wire \result[17]_i_2_n_0 ;
  wire \result[17]_i_3_n_0 ;
  wire \result[17]_i_4_n_0 ;
  wire \result[17]_i_5_n_0 ;
  wire \result[17]_i_6_n_0 ;
  wire \result[17]_i_7_n_0 ;
  wire \result[17]_i_8_n_0 ;
  wire \result[18]_i_1_n_0 ;
  wire \result[18]_i_2_n_0 ;
  wire \result[18]_i_3_n_0 ;
  wire \result[18]_i_4_n_0 ;
  wire \result[18]_i_5_n_0 ;
  wire \result[18]_i_6_n_0 ;
  wire \result[18]_i_7_n_0 ;
  wire \result[18]_i_8_n_0 ;
  wire \result[19]_i_10_n_0 ;
  wire \result[19]_i_12_n_0 ;
  wire \result[19]_i_13_n_0 ;
  wire \result[19]_i_14_n_0 ;
  wire \result[19]_i_15_n_0 ;
  wire \result[19]_i_16_n_0 ;
  wire \result[19]_i_17_n_0 ;
  wire \result[19]_i_18_n_0 ;
  wire \result[19]_i_19_n_0 ;
  wire \result[19]_i_1_n_0 ;
  wire \result[19]_i_20_n_0 ;
  wire \result[19]_i_21_n_0 ;
  wire \result[19]_i_22_n_0 ;
  wire \result[19]_i_23_n_0 ;
  wire \result[19]_i_2_n_0 ;
  wire \result[19]_i_3_n_0 ;
  wire \result[19]_i_4_n_0 ;
  wire \result[19]_i_5_n_0 ;
  wire \result[19]_i_8_n_0 ;
  wire \result[19]_i_9_n_0 ;
  wire \result[1]_i_10_n_0 ;
  wire \result[1]_i_11_n_0 ;
  wire \result[1]_i_12_n_0 ;
  wire \result[1]_i_13_n_0 ;
  wire \result[1]_i_1_n_0 ;
  wire \result[1]_i_2_n_0 ;
  wire \result[1]_i_3_n_0 ;
  wire \result[1]_i_4_n_0 ;
  wire \result[1]_i_5_n_0 ;
  wire \result[1]_i_7_n_0 ;
  wire \result[1]_i_8_n_0 ;
  wire \result[1]_i_9_n_0 ;
  wire \result[20]_i_1_n_0 ;
  wire \result[20]_i_2_n_0 ;
  wire \result[20]_i_3_n_0 ;
  wire \result[20]_i_4_n_0 ;
  wire \result[20]_i_5_n_0 ;
  wire \result[20]_i_6_n_0 ;
  wire \result[20]_i_7_n_0 ;
  wire \result[20]_i_8_n_0 ;
  wire \result[21]_i_1_n_0 ;
  wire \result[21]_i_2_n_0 ;
  wire \result[21]_i_3_n_0 ;
  wire \result[21]_i_4_n_0 ;
  wire \result[21]_i_5_n_0 ;
  wire \result[21]_i_6_n_0 ;
  wire \result[21]_i_7_n_0 ;
  wire \result[21]_i_8_n_0 ;
  wire \result[22]_i_1_n_0 ;
  wire \result[22]_i_2_n_0 ;
  wire \result[22]_i_3_n_0 ;
  wire \result[22]_i_4_n_0 ;
  wire \result[22]_i_5_n_0 ;
  wire \result[22]_i_6_n_0 ;
  wire \result[22]_i_7_n_0 ;
  wire \result[22]_i_8_n_0 ;
  wire \result[23]_i_11_n_0 ;
  wire \result[23]_i_12_n_0 ;
  wire \result[23]_i_13_n_0 ;
  wire \result[23]_i_14_n_0 ;
  wire \result[23]_i_15_n_0 ;
  wire \result[23]_i_16_n_0 ;
  wire \result[23]_i_17_n_0 ;
  wire \result[23]_i_18_n_0 ;
  wire \result[23]_i_19_n_0 ;
  wire \result[23]_i_1_n_0 ;
  wire \result[23]_i_20_n_0 ;
  wire \result[23]_i_21_n_0 ;
  wire \result[23]_i_22_n_0 ;
  wire \result[23]_i_23_n_0 ;
  wire \result[23]_i_2_n_0 ;
  wire \result[23]_i_3_n_0 ;
  wire \result[23]_i_4_n_0 ;
  wire \result[23]_i_5_n_0 ;
  wire \result[23]_i_6_n_0 ;
  wire \result[23]_i_9_n_0 ;
  wire \result[24]_i_1_n_0 ;
  wire \result[24]_i_2_n_0 ;
  wire \result[24]_i_3_n_0 ;
  wire \result[24]_i_4_n_0 ;
  wire \result[24]_i_5_n_0 ;
  wire \result[24]_i_6_n_0 ;
  wire \result[24]_i_7_n_0 ;
  wire \result[24]_i_8_n_0 ;
  wire \result[25]_i_1_n_0 ;
  wire \result[25]_i_2_n_0 ;
  wire \result[25]_i_3_n_0 ;
  wire \result[25]_i_4_n_0 ;
  wire \result[25]_i_5_n_0 ;
  wire \result[25]_i_6_n_0 ;
  wire \result[25]_i_7_n_0 ;
  wire \result[25]_i_8_n_0 ;
  wire \result[26]_i_1_n_0 ;
  wire \result[26]_i_2_n_0 ;
  wire \result[26]_i_3_n_0 ;
  wire \result[26]_i_4_n_0 ;
  wire \result[26]_i_5_n_0 ;
  wire \result[26]_i_6_n_0 ;
  wire \result[26]_i_7_n_0 ;
  wire \result[26]_i_8_n_0 ;
  wire \result[27]_i_12_n_0 ;
  wire \result[27]_i_13_n_0 ;
  wire \result[27]_i_14_n_0 ;
  wire \result[27]_i_15_n_0 ;
  wire \result[27]_i_16_n_0 ;
  wire \result[27]_i_17_n_0 ;
  wire \result[27]_i_18_n_0 ;
  wire \result[27]_i_19_n_0 ;
  wire \result[27]_i_1_n_0 ;
  wire \result[27]_i_20_n_0 ;
  wire \result[27]_i_21_n_0 ;
  wire \result[27]_i_22_n_0 ;
  wire \result[27]_i_23_n_0 ;
  wire \result[27]_i_24_n_0 ;
  wire \result[27]_i_25_n_0 ;
  wire \result[27]_i_26_n_0 ;
  wire \result[27]_i_27_n_0 ;
  wire \result[27]_i_28_n_0 ;
  wire \result[27]_i_29_n_0 ;
  wire \result[27]_i_2_n_0 ;
  wire \result[27]_i_30_n_0 ;
  wire \result[27]_i_31_n_0 ;
  wire \result[27]_i_32_n_0 ;
  wire \result[27]_i_33_n_0 ;
  wire \result[27]_i_34_n_0 ;
  wire \result[27]_i_3_n_0 ;
  wire \result[27]_i_4_n_0 ;
  wire \result[27]_i_5_n_0 ;
  wire \result[27]_i_6_n_0 ;
  wire \result[27]_i_7_n_0 ;
  wire \result[27]_i_8_n_0 ;
  wire \result[27]_i_9_n_0 ;
  wire \result[28]_i_10_n_0 ;
  wire \result[28]_i_1_n_0 ;
  wire \result[28]_i_2_n_0 ;
  wire \result[28]_i_4_n_0 ;
  wire \result[28]_i_5_n_0 ;
  wire \result[28]_i_6_n_0 ;
  wire \result[28]_i_7_n_0 ;
  wire \result[28]_i_9_n_0 ;
  wire \result[29]_i_10_n_0 ;
  wire \result[29]_i_11_n_0 ;
  wire \result[29]_i_1_n_0 ;
  wire \result[29]_i_2_n_0 ;
  wire \result[29]_i_4_n_0 ;
  wire \result[29]_i_5_n_0 ;
  wire \result[29]_i_6_n_0 ;
  wire \result[29]_i_7_n_0 ;
  wire \result[29]_i_8_n_0 ;
  wire \result[29]_i_9_n_0 ;
  wire \result[2]_i_1_n_0 ;
  wire \result[2]_i_2_n_0 ;
  wire \result[2]_i_3_n_0 ;
  wire \result[2]_i_4_n_0 ;
  wire \result[2]_i_5_n_0 ;
  wire \result[2]_i_6_n_0 ;
  wire \result[2]_i_7_n_0 ;
  wire \result[30]_i_10_n_0 ;
  wire \result[30]_i_11_n_0 ;
  wire \result[30]_i_1_n_0 ;
  wire \result[30]_i_2_n_0 ;
  wire \result[30]_i_4_n_0 ;
  wire \result[30]_i_5_n_0 ;
  wire \result[30]_i_6_n_0 ;
  wire \result[30]_i_7_n_0 ;
  wire \result[30]_i_8_n_0 ;
  wire \result[30]_i_9_n_0 ;
  wire \result[31]_i_10_n_0 ;
  wire \result[31]_i_11_n_0 ;
  wire \result[31]_i_12_n_0 ;
  wire \result[31]_i_13_n_0 ;
  wire \result[31]_i_17_n_0 ;
  wire \result[31]_i_18_n_0 ;
  wire \result[31]_i_19_n_0 ;
  wire \result[31]_i_1_n_0 ;
  wire \result[31]_i_20_n_0 ;
  wire \result[31]_i_21_n_0 ;
  wire \result[31]_i_22_n_0 ;
  wire \result[31]_i_23_n_0 ;
  wire \result[31]_i_24_n_0 ;
  wire \result[31]_i_25_n_0 ;
  wire \result[31]_i_26_n_0 ;
  wire \result[31]_i_27_n_0 ;
  wire \result[31]_i_28_n_0 ;
  wire \result[31]_i_29_n_0 ;
  wire \result[31]_i_2_n_0 ;
  wire \result[31]_i_30_n_0 ;
  wire \result[31]_i_31_n_0 ;
  wire \result[31]_i_32_n_0 ;
  wire \result[31]_i_33_n_0 ;
  wire \result[31]_i_34_n_0 ;
  wire \result[31]_i_35_n_0 ;
  wire \result[31]_i_36_n_0 ;
  wire \result[31]_i_37_n_0 ;
  wire \result[31]_i_38_n_0 ;
  wire \result[31]_i_39_n_0 ;
  wire \result[31]_i_3_n_0 ;
  wire \result[31]_i_40_n_0 ;
  wire \result[31]_i_41_n_0 ;
  wire \result[31]_i_4_n_0 ;
  wire \result[31]_i_5_n_0 ;
  wire \result[31]_i_7_n_0 ;
  wire \result[31]_i_8_n_0 ;
  wire \result[3]_i_10_n_0 ;
  wire \result[3]_i_11_n_0 ;
  wire \result[3]_i_12_n_0 ;
  wire \result[3]_i_13_n_0 ;
  wire \result[3]_i_14_n_0 ;
  wire \result[3]_i_15_n_0 ;
  wire \result[3]_i_16_n_0 ;
  wire \result[3]_i_17_n_0 ;
  wire \result[3]_i_1_n_0 ;
  wire \result[3]_i_2_n_0 ;
  wire \result[3]_i_3_n_0 ;
  wire \result[3]_i_4_n_0 ;
  wire \result[3]_i_5_n_0 ;
  wire \result[3]_i_6_n_0 ;
  wire \result[3]_i_7_n_0 ;
  wire \result[4]_i_1_n_0 ;
  wire \result[4]_i_2_n_0 ;
  wire \result[4]_i_3_n_0 ;
  wire \result[4]_i_4_n_0 ;
  wire \result[4]_i_5_n_0 ;
  wire \result[4]_i_6_n_0 ;
  wire \result[4]_i_7_n_0 ;
  wire \result[5]_i_1_n_0 ;
  wire \result[5]_i_2_n_0 ;
  wire \result[5]_i_3_n_0 ;
  wire \result[5]_i_4_n_0 ;
  wire \result[5]_i_5_n_0 ;
  wire \result[5]_i_6_n_0 ;
  wire \result[5]_i_7_n_0 ;
  wire \result[6]_i_1_n_0 ;
  wire \result[6]_i_2_n_0 ;
  wire \result[6]_i_3_n_0 ;
  wire \result[6]_i_4_n_0 ;
  wire \result[6]_i_5_n_0 ;
  wire \result[6]_i_6_n_0 ;
  wire \result[6]_i_7_n_0 ;
  wire \result[7]_i_12_n_0 ;
  wire \result[7]_i_13_n_0 ;
  wire \result[7]_i_14_n_0 ;
  wire \result[7]_i_15_n_0 ;
  wire \result[7]_i_16_n_0 ;
  wire \result[7]_i_17_n_0 ;
  wire \result[7]_i_18_n_0 ;
  wire \result[7]_i_19_n_0 ;
  wire \result[7]_i_1_n_0 ;
  wire \result[7]_i_20_n_0 ;
  wire \result[7]_i_21_n_0 ;
  wire \result[7]_i_22_n_0 ;
  wire \result[7]_i_23_n_0 ;
  wire \result[7]_i_2_n_0 ;
  wire \result[7]_i_3_n_0 ;
  wire \result[7]_i_4_n_0 ;
  wire \result[7]_i_5_n_0 ;
  wire \result[7]_i_6_n_0 ;
  wire \result[7]_i_7_n_0 ;
  wire \result[7]_i_8_n_0 ;
  wire \result[8]_i_1_n_0 ;
  wire \result[8]_i_2_n_0 ;
  wire \result[8]_i_3_n_0 ;
  wire \result[8]_i_4_n_0 ;
  wire \result[8]_i_5_n_0 ;
  wire \result[8]_i_6_n_0 ;
  wire \result[8]_i_7_n_0 ;
  wire \result[9]_i_1_n_0 ;
  wire \result[9]_i_2_n_0 ;
  wire \result[9]_i_3_n_0 ;
  wire \result[9]_i_4_n_0 ;
  wire \result[9]_i_5_n_0 ;
  wire \result[9]_i_6_n_0 ;
  wire \result[9]_i_7_n_0 ;
  wire \result_reg[0]_i_14_n_0 ;
  wire \result_reg[0]_i_23_n_0 ;
  wire \result_reg[0]_i_29_n_0 ;
  wire \result_reg[0]_i_33_n_0 ;
  wire \result_reg[0]_i_38_n_0 ;
  wire \result_reg[0]_i_52_n_0 ;
  wire \result_reg[0]_i_57_n_0 ;
  wire \result_reg[0]_i_64_n_0 ;
  wire \result_reg[0]_i_69_n_0 ;
  wire \result_reg[0]_i_82_n_0 ;
  wire \result_reg[0]_i_95_n_0 ;
  wire \result_reg[11]_i_8_n_0 ;
  wire \result_reg[11]_i_8_n_4 ;
  wire \result_reg[11]_i_8_n_5 ;
  wire \result_reg[11]_i_8_n_6 ;
  wire \result_reg[11]_i_8_n_7 ;
  wire \result_reg[15]_i_10_n_0 ;
  wire \result_reg[15]_i_10_n_4 ;
  wire \result_reg[15]_i_10_n_5 ;
  wire \result_reg[15]_i_10_n_6 ;
  wire \result_reg[15]_i_10_n_7 ;
  wire \result_reg[15]_i_11_n_0 ;
  wire \result_reg[15]_i_16_n_0 ;
  wire \result_reg[15]_i_16_n_4 ;
  wire \result_reg[15]_i_16_n_5 ;
  wire \result_reg[15]_i_16_n_6 ;
  wire \result_reg[15]_i_16_n_7 ;
  wire \result_reg[15]_i_7_n_0 ;
  wire \result_reg[15]_i_8_n_0 ;
  wire \result_reg[15]_i_8_n_4 ;
  wire \result_reg[15]_i_8_n_5 ;
  wire \result_reg[15]_i_8_n_6 ;
  wire \result_reg[15]_i_8_n_7 ;
  wire \result_reg[16]_i_10_n_0 ;
  wire \result_reg[19]_i_11_n_0 ;
  wire \result_reg[19]_i_11_n_4 ;
  wire \result_reg[19]_i_11_n_5 ;
  wire \result_reg[19]_i_11_n_6 ;
  wire \result_reg[19]_i_11_n_7 ;
  wire \result_reg[19]_i_6_n_0 ;
  wire \result_reg[19]_i_7_n_0 ;
  wire \result_reg[19]_i_7_n_4 ;
  wire \result_reg[19]_i_7_n_5 ;
  wire \result_reg[19]_i_7_n_6 ;
  wire \result_reg[19]_i_7_n_7 ;
  wire \result_reg[1]_i_6_n_0 ;
  wire \result_reg[1]_i_6_n_4 ;
  wire \result_reg[1]_i_6_n_5 ;
  wire \result_reg[1]_i_6_n_6 ;
  wire \result_reg[1]_i_6_n_7 ;
  wire \result_reg[23]_i_10_n_0 ;
  wire \result_reg[23]_i_10_n_4 ;
  wire \result_reg[23]_i_10_n_5 ;
  wire \result_reg[23]_i_10_n_6 ;
  wire \result_reg[23]_i_10_n_7 ;
  wire \result_reg[23]_i_7_n_0 ;
  wire \result_reg[23]_i_7_n_4 ;
  wire \result_reg[23]_i_7_n_5 ;
  wire \result_reg[23]_i_7_n_6 ;
  wire \result_reg[23]_i_7_n_7 ;
  wire \result_reg[23]_i_8_n_0 ;
  wire \result_reg[27]_i_10_n_0 ;
  wire \result_reg[27]_i_10_n_4 ;
  wire \result_reg[27]_i_10_n_5 ;
  wire \result_reg[27]_i_10_n_6 ;
  wire \result_reg[27]_i_10_n_7 ;
  wire \result_reg[27]_i_11_n_0 ;
  wire \result_reg[28]_i_3_n_0 ;
  wire \result_reg[29]_i_3_n_0 ;
  wire \result_reg[30]_i_3_n_0 ;
  wire \result_reg[31]_i_15_n_4 ;
  wire \result_reg[31]_i_15_n_5 ;
  wire \result_reg[31]_i_15_n_6 ;
  wire \result_reg[31]_i_15_n_7 ;
  wire \result_reg[31]_i_16_n_0 ;
  wire \result_reg[31]_i_16_n_4 ;
  wire \result_reg[31]_i_16_n_5 ;
  wire \result_reg[31]_i_16_n_6 ;
  wire \result_reg[31]_i_16_n_7 ;
  wire \result_reg[31]_i_6_n_0 ;
  wire \result_reg[31]_i_9_n_4 ;
  wire \result_reg[31]_i_9_n_5 ;
  wire \result_reg[31]_i_9_n_6 ;
  wire \result_reg[31]_i_9_n_7 ;
  wire \result_reg[3]_i_8_n_0 ;
  wire \result_reg[3]_i_9_n_0 ;
  wire \result_reg[3]_i_9_n_4 ;
  wire \result_reg[3]_i_9_n_5 ;
  wire \result_reg[3]_i_9_n_6 ;
  wire \result_reg[3]_i_9_n_7 ;
  wire \result_reg[4]_i_8_n_0 ;
  wire \result_reg[7]_i_10_n_0 ;
  wire \result_reg[7]_i_11_n_0 ;
  wire \result_reg[7]_i_11_n_4 ;
  wire \result_reg[7]_i_11_n_5 ;
  wire \result_reg[7]_i_11_n_6 ;
  wire \result_reg[7]_i_11_n_7 ;
  wire \result_reg[7]_i_9_n_0 ;
  wire \result_reg[7]_i_9_n_4 ;
  wire \result_reg[7]_i_9_n_5 ;
  wire \result_reg[7]_i_9_n_6 ;
  wire \result_reg[7]_i_9_n_7 ;
  wire \result_reg[8]_i_8_n_0 ;
  wire \s_input_rs232_in_ack[0]_i_1_n_0 ;
  wire \s_input_rs232_in_ack[0]_i_2_n_0 ;
  wire \s_input_rs232_in_ack[0]_i_3_n_0 ;
  wire \s_input_rs232_in_ack[0]_i_4_n_0 ;
  wire \s_input_rs232_in_ack[0]_i_5_n_0 ;
  wire \s_input_rs232_in_ack[0]_i_6_n_0 ;
  wire \s_input_rs232_in_ack[0]_i_7_n_0 ;
  wire \s_input_rs232_in_ack[0]_i_8_n_0 ;
  wire \s_output_rs232_out[7]_i_1_n_0 ;
  wire \s_output_rs232_out[7]_i_2_n_0 ;
  wire \s_output_rs232_out[7]_i_3_n_0 ;
  wire \s_output_rs232_out[7]_i_4_n_0 ;
  wire \s_output_rs232_out[7]_i_5_n_0 ;
  wire \s_output_rs232_out[7]_i_6_n_0 ;
  wire \s_output_rs232_out[7]_i_7_n_0 ;
  wire \s_output_rs232_out[7]_i_8_n_0 ;
  wire \s_output_rs232_out_stb[0]_i_1_n_0 ;
  wire [15:0]sel;
  wire \state[0]_i_1_n_0 ;
  wire \state[0]_i_2_n_0 ;
  wire \state[0]_i_3_n_0 ;
  wire \state[1]_i_1_n_0 ;
  wire \state[1]_i_2_n_0 ;
  wire \state[2]_i_1_n_0 ;
  wire \state[2]_i_2_n_0 ;
  wire \state[2]_i_3_n_0 ;
  wire \state[2]_i_4_n_0 ;
  wire \state[2]_i_5_n_0 ;
  wire \state[2]_i_6_n_0 ;
  wire \state_reg_n_0_[0] ;
  wire \state_reg_n_0_[1] ;
  wire \state_reg_n_0_[2] ;
  wire [31:0]store_data;
  wire write_enable_reg_n_0;
  wire [31:0]write_output;
  wire [7:0]write_value;
  wire \write_value[7]_i_2_n_0 ;
  wire \write_value[7]_i_3_n_0 ;
  wire NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED;
  wire NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED;
  wire NLW_memory_reg_0_DBITERR_UNCONNECTED;
  wire NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED;
  wire NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED;
  wire NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED;
  wire NLW_memory_reg_0_REGCEB_UNCONNECTED;
  wire NLW_memory_reg_0_SBITERR_UNCONNECTED;
  wire [31:4]NLW_memory_reg_0_DOADO_UNCONNECTED;
  wire [31:0]NLW_memory_reg_0_DOBDO_UNCONNECTED;
  wire [3:0]NLW_memory_reg_0_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_memory_reg_0_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_memory_reg_0_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_memory_reg_0_RDADDRECC_UNCONNECTED;
  wire NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED;
  wire NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED;
  wire NLW_memory_reg_1_DBITERR_UNCONNECTED;
  wire NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED;
  wire NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED;
  wire NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED;
  wire NLW_memory_reg_1_REGCEB_UNCONNECTED;
  wire NLW_memory_reg_1_SBITERR_UNCONNECTED;
  wire [31:4]NLW_memory_reg_1_DOADO_UNCONNECTED;
  wire [31:0]NLW_memory_reg_1_DOBDO_UNCONNECTED;
  wire [3:0]NLW_memory_reg_1_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_memory_reg_1_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_memory_reg_1_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_memory_reg_1_RDADDRECC_UNCONNECTED;
  wire NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED;
  wire NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED;
  wire NLW_memory_reg_2_DBITERR_UNCONNECTED;
  wire NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED;
  wire NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED;
  wire NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED;
  wire NLW_memory_reg_2_REGCEB_UNCONNECTED;
  wire NLW_memory_reg_2_SBITERR_UNCONNECTED;
  wire [31:4]NLW_memory_reg_2_DOADO_UNCONNECTED;
  wire [31:0]NLW_memory_reg_2_DOBDO_UNCONNECTED;
  wire [3:0]NLW_memory_reg_2_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_memory_reg_2_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_memory_reg_2_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_memory_reg_2_RDADDRECC_UNCONNECTED;
  wire NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED;
  wire NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED;
  wire NLW_memory_reg_3_DBITERR_UNCONNECTED;
  wire NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED;
  wire NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED;
  wire NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED;
  wire NLW_memory_reg_3_REGCEB_UNCONNECTED;
  wire NLW_memory_reg_3_SBITERR_UNCONNECTED;
  wire [31:4]NLW_memory_reg_3_DOADO_UNCONNECTED;
  wire [31:0]NLW_memory_reg_3_DOBDO_UNCONNECTED;
  wire [3:0]NLW_memory_reg_3_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_memory_reg_3_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_memory_reg_3_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_memory_reg_3_RDADDRECC_UNCONNECTED;
  wire NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED;
  wire NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED;
  wire NLW_memory_reg_4_DBITERR_UNCONNECTED;
  wire NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED;
  wire NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED;
  wire NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED;
  wire NLW_memory_reg_4_REGCEB_UNCONNECTED;
  wire NLW_memory_reg_4_SBITERR_UNCONNECTED;
  wire [31:4]NLW_memory_reg_4_DOADO_UNCONNECTED;
  wire [31:0]NLW_memory_reg_4_DOBDO_UNCONNECTED;
  wire [3:0]NLW_memory_reg_4_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_memory_reg_4_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_memory_reg_4_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_memory_reg_4_RDADDRECC_UNCONNECTED;
  wire NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED;
  wire NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED;
  wire NLW_memory_reg_5_DBITERR_UNCONNECTED;
  wire NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED;
  wire NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED;
  wire NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED;
  wire NLW_memory_reg_5_REGCEB_UNCONNECTED;
  wire NLW_memory_reg_5_SBITERR_UNCONNECTED;
  wire [31:4]NLW_memory_reg_5_DOADO_UNCONNECTED;
  wire [31:0]NLW_memory_reg_5_DOBDO_UNCONNECTED;
  wire [3:0]NLW_memory_reg_5_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_memory_reg_5_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_memory_reg_5_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_memory_reg_5_RDADDRECC_UNCONNECTED;
  wire NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED;
  wire NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED;
  wire NLW_memory_reg_6_DBITERR_UNCONNECTED;
  wire NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED;
  wire NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED;
  wire NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED;
  wire NLW_memory_reg_6_REGCEB_UNCONNECTED;
  wire NLW_memory_reg_6_SBITERR_UNCONNECTED;
  wire [31:4]NLW_memory_reg_6_DOADO_UNCONNECTED;
  wire [31:0]NLW_memory_reg_6_DOBDO_UNCONNECTED;
  wire [3:0]NLW_memory_reg_6_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_memory_reg_6_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_memory_reg_6_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_memory_reg_6_RDADDRECC_UNCONNECTED;
  wire NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED;
  wire NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED;
  wire NLW_memory_reg_7_DBITERR_UNCONNECTED;
  wire NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED;
  wire NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED;
  wire NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED;
  wire NLW_memory_reg_7_REGCEB_UNCONNECTED;
  wire NLW_memory_reg_7_SBITERR_UNCONNECTED;
  wire [31:4]NLW_memory_reg_7_DOADO_UNCONNECTED;
  wire [31:0]NLW_memory_reg_7_DOBDO_UNCONNECTED;
  wire [3:0]NLW_memory_reg_7_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_memory_reg_7_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_memory_reg_7_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_memory_reg_7_RDADDRECC_UNCONNECTED;
  wire [2:0]\NLW_program_counter_reg[12]_i_2_CO_UNCONNECTED ;
  wire [3:0]\NLW_program_counter_reg[15]_i_4_CO_UNCONNECTED ;
  wire [3:3]\NLW_program_counter_reg[15]_i_4_O_UNCONNECTED ;
  wire [2:0]\NLW_program_counter_reg[4]_i_2_CO_UNCONNECTED ;
  wire [2:0]\NLW_program_counter_reg[8]_i_2_CO_UNCONNECTED ;
  wire NLW_program_counter_reg_rep_0_CASCADEOUTA_UNCONNECTED;
  wire NLW_program_counter_reg_rep_0_CASCADEOUTB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_0_DBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_0_INJECTDBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_0_INJECTSBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_0_REGCEB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_0_SBITERR_UNCONNECTED;
  wire [31:4]NLW_program_counter_reg_rep_0_DOADO_UNCONNECTED;
  wire [31:0]NLW_program_counter_reg_rep_0_DOBDO_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_0_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_0_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_program_counter_reg_rep_0_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_program_counter_reg_rep_0_RDADDRECC_UNCONNECTED;
  wire NLW_program_counter_reg_rep_1_CASCADEOUTA_UNCONNECTED;
  wire NLW_program_counter_reg_rep_1_CASCADEOUTB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_1_DBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_1_INJECTDBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_1_INJECTSBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_1_REGCEB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_1_SBITERR_UNCONNECTED;
  wire [31:4]NLW_program_counter_reg_rep_1_DOADO_UNCONNECTED;
  wire [31:0]NLW_program_counter_reg_rep_1_DOBDO_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_1_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_1_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_program_counter_reg_rep_1_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_program_counter_reg_rep_1_RDADDRECC_UNCONNECTED;
  wire NLW_program_counter_reg_rep_2_CASCADEOUTA_UNCONNECTED;
  wire NLW_program_counter_reg_rep_2_CASCADEOUTB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_2_DBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_2_INJECTDBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_2_INJECTSBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_2_REGCEB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_2_SBITERR_UNCONNECTED;
  wire [31:4]NLW_program_counter_reg_rep_2_DOADO_UNCONNECTED;
  wire [31:0]NLW_program_counter_reg_rep_2_DOBDO_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_2_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_2_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_program_counter_reg_rep_2_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_program_counter_reg_rep_2_RDADDRECC_UNCONNECTED;
  wire NLW_program_counter_reg_rep_3_CASCADEOUTA_UNCONNECTED;
  wire NLW_program_counter_reg_rep_3_CASCADEOUTB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_3_DBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_3_INJECTDBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_3_INJECTSBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_3_REGCEB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_3_SBITERR_UNCONNECTED;
  wire [31:4]NLW_program_counter_reg_rep_3_DOADO_UNCONNECTED;
  wire [31:0]NLW_program_counter_reg_rep_3_DOBDO_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_3_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_3_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_program_counter_reg_rep_3_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_program_counter_reg_rep_3_RDADDRECC_UNCONNECTED;
  wire NLW_program_counter_reg_rep_4_CASCADEOUTA_UNCONNECTED;
  wire NLW_program_counter_reg_rep_4_CASCADEOUTB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_4_DBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_4_INJECTDBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_4_INJECTSBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_4_REGCEB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_4_SBITERR_UNCONNECTED;
  wire [31:4]NLW_program_counter_reg_rep_4_DOADO_UNCONNECTED;
  wire [31:0]NLW_program_counter_reg_rep_4_DOBDO_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_4_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_4_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_program_counter_reg_rep_4_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_program_counter_reg_rep_4_RDADDRECC_UNCONNECTED;
  wire NLW_program_counter_reg_rep_5_CASCADEOUTA_UNCONNECTED;
  wire NLW_program_counter_reg_rep_5_CASCADEOUTB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_5_DBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_5_INJECTDBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_5_INJECTSBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_5_REGCEB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_5_SBITERR_UNCONNECTED;
  wire [31:4]NLW_program_counter_reg_rep_5_DOADO_UNCONNECTED;
  wire [31:0]NLW_program_counter_reg_rep_5_DOBDO_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_5_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_5_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_program_counter_reg_rep_5_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_program_counter_reg_rep_5_RDADDRECC_UNCONNECTED;
  wire NLW_program_counter_reg_rep_6_CASCADEOUTA_UNCONNECTED;
  wire NLW_program_counter_reg_rep_6_CASCADEOUTB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_6_DBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_6_INJECTDBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_6_INJECTSBITERR_UNCONNECTED;
  wire NLW_program_counter_reg_rep_6_REGCEB_UNCONNECTED;
  wire NLW_program_counter_reg_rep_6_SBITERR_UNCONNECTED;
  wire [31:4]NLW_program_counter_reg_rep_6_DOADO_UNCONNECTED;
  wire [31:0]NLW_program_counter_reg_rep_6_DOBDO_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_6_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_program_counter_reg_rep_6_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_program_counter_reg_rep_6_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_program_counter_reg_rep_6_RDADDRECC_UNCONNECTED;
  wire NLW_program_counter_reg_rep_7_REGCEB_UNCONNECTED;
  wire [15:1]NLW_program_counter_reg_rep_7_DOADO_UNCONNECTED;
  wire [15:0]NLW_program_counter_reg_rep_7_DOBDO_UNCONNECTED;
  wire [1:0]NLW_program_counter_reg_rep_7_DOPADOP_UNCONNECTED;
  wire [1:0]NLW_program_counter_reg_rep_7_DOPBDOP_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED;
  wire [1:0]NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED;
  wire [2:0]\NLW_result_reg[0]_i_10_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_10_O_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_12_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_12_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_13_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_13_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_14_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_14_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_23_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_23_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_29_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_29_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_33_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_33_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_38_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_38_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_52_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_52_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_57_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_57_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_64_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_64_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_69_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_69_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_7_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_7_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_82_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_82_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[0]_i_95_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[0]_i_95_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[11]_i_8_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[15]_i_10_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[15]_i_11_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[15]_i_16_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[15]_i_7_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[15]_i_8_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[16]_i_10_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[16]_i_7_CO_UNCONNECTED ;
  wire [3:3]\NLW_result_reg[16]_i_7_O_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[19]_i_11_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[19]_i_6_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[19]_i_7_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[1]_i_6_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[23]_i_10_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[23]_i_7_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[23]_i_8_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[27]_i_10_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[27]_i_11_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[31]_i_14_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[31]_i_15_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[31]_i_16_CO_UNCONNECTED ;
  wire [3:0]\NLW_result_reg[31]_i_9_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[3]_i_8_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[3]_i_9_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[4]_i_8_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[7]_i_10_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[7]_i_11_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[7]_i_9_CO_UNCONNECTED ;
  wire [2:0]\NLW_result_reg[8]_i_8_CO_UNCONNECTED ;

  FDRE \address_a_2_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(address_a[0]),
        .Q(address_a_2[0]),
        .R(1'b0));
  FDRE \address_a_2_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(address_a[1]),
        .Q(address_a_2[1]),
        .R(1'b0));
  FDRE \address_a_2_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(address_a[2]),
        .Q(address_a_2[2]),
        .R(1'b0));
  FDRE \address_a_2_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(address_a[3]),
        .Q(address_a_2[3]),
        .R(1'b0));
  FDRE \address_b_2_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_0_n_35),
        .Q(address_b_2[0]),
        .R(1'b0));
  FDRE \address_b_2_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_0_n_34),
        .Q(address_b_2[1]),
        .R(1'b0));
  FDRE \address_b_2_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_0_n_33),
        .Q(address_b_2[2]),
        .R(1'b0));
  FDRE \address_b_2_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_0_n_32),
        .Q(address_b_2[3]),
        .R(1'b0));
  FDRE \address_z_2_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(address_z[0]),
        .Q(address_z_2[0]),
        .R(1'b0));
  FDRE \address_z_2_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(address_z[1]),
        .Q(address_z_2[1]),
        .R(1'b0));
  FDRE \address_z_2_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(address_z[2]),
        .Q(address_z_2[2]),
        .R(1'b0));
  FDRE \address_z_2_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(address_z[3]),
        .Q(address_z_2[3]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h40)) 
    \address_z_3[3]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(\state_reg_n_0_[0] ),
        .O(\address_z_3[3]_i_1_n_0 ));
  FDRE \address_z_3_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\address_z_3[3]_i_1_n_0 ),
        .D(address_z_2[0]),
        .Q(address_z_3[0]),
        .R(INTERNAL_RST_reg));
  FDRE \address_z_3_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\address_z_3[3]_i_1_n_0 ),
        .D(address_z_2[1]),
        .Q(address_z_3[1]),
        .R(INTERNAL_RST_reg));
  FDRE \address_z_3_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\address_z_3[3]_i_1_n_0 ),
        .D(address_z_2[2]),
        .Q(address_z_3[2]),
        .R(INTERNAL_RST_reg));
  FDRE \address_z_3_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\address_z_3[3]_i_1_n_0 ),
        .D(address_z_2[3]),
        .Q(address_z_3[3]),
        .R(INTERNAL_RST_reg));
  LUT2 #(
    .INIT(4'h2)) 
    \literal_2[15]_i_1 
       (.I0(\state_reg_n_0_[1] ),
        .I1(\state_reg_n_0_[2] ),
        .O(opcode_20));
  FDRE \literal_2_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_2_n_33),
        .Q(data7[26]),
        .R(1'b0));
  FDRE \literal_2_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_2_n_32),
        .Q(data7[27]),
        .R(1'b0));
  FDRE \literal_2_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_3_n_35),
        .Q(data7[28]),
        .R(1'b0));
  FDRE \literal_2_reg[13] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_3_n_34),
        .Q(data7[29]),
        .R(1'b0));
  FDRE \literal_2_reg[14] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_3_n_33),
        .Q(data7[30]),
        .R(1'b0));
  FDRE \literal_2_reg[15] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_3_n_32),
        .Q(data7[31]),
        .R(1'b0));
  FDRE \literal_2_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_1_n_35),
        .Q(data7[20]),
        .R(1'b0));
  FDRE \literal_2_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_1_n_34),
        .Q(data7[21]),
        .R(1'b0));
  FDRE \literal_2_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_1_n_33),
        .Q(data7[22]),
        .R(1'b0));
  FDRE \literal_2_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_1_n_32),
        .Q(data7[23]),
        .R(1'b0));
  FDRE \literal_2_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_2_n_35),
        .Q(data7[24]),
        .R(1'b0));
  FDRE \literal_2_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_reg_rep_2_n_34),
        .Q(data7[25]),
        .R(1'b0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* RTL_RAM_BITS = "131104" *) 
  (* RTL_RAM_NAME = "memory" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "0" *) 
  (* bram_slice_end = "3" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    memory_reg_0
       (.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_memory_reg_0_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[3:0]}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_memory_reg_0_DOADO_UNCONNECTED[31:4],load_data[3:0]}),
        .DOBDO(NLW_memory_reg_0_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_memory_reg_0_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_memory_reg_0_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_memory_reg_0_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(1'b1),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_memory_reg_0_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_memory_reg_0_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_memory_reg_0_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT6 #(
    .INIT(64'h0000000002000000)) 
    memory_reg_0_i_1
       (.I0(opcode_2[1]),
        .I1(opcode_2[2]),
        .I2(opcode_2[0]),
        .I3(opcode_20),
        .I4(\state_reg_n_0_[0] ),
        .I5(memory_reg_0_i_2_n_0),
        .O(memory_reg_0_i_1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    memory_reg_0_i_2
       (.I0(opcode_2[4]),
        .I1(opcode_2[3]),
        .O(memory_reg_0_i_2_n_0));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENARDEN=NEW" *) 
  (* RTL_RAM_BITS = "131104" *) 
  (* RTL_RAM_NAME = "memory" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "4" *) 
  (* bram_slice_end = "7" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    memory_reg_1
       (.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_memory_reg_1_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[7:4]}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_memory_reg_1_DOADO_UNCONNECTED[31:4],load_data[7:4]}),
        .DOBDO(NLW_memory_reg_1_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_memory_reg_1_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_memory_reg_1_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_memory_reg_1_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(memory_reg_1_ENARDEN_cooolgate_en_sig_1),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_memory_reg_1_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_memory_reg_1_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_memory_reg_1_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT4 #(
    .INIT(16'hff02)) 
    memory_reg_1_ENARDEN_cooolgate_en_gate_1
       (.I0(\state[2]_i_1_n_0 ),
        .I1(\state[1]_i_1_n_0 ),
        .I2(INTERNAL_RST_reg),
        .I3(memory_reg_0_i_1_n_0),
        .O(memory_reg_1_ENARDEN_cooolgate_en_sig_1));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENARDEN=NEW" *) 
  (* RTL_RAM_BITS = "131104" *) 
  (* RTL_RAM_NAME = "memory" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "8" *) 
  (* bram_slice_end = "11" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    memory_reg_2
       (.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_memory_reg_2_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[11:8]}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_memory_reg_2_DOADO_UNCONNECTED[31:4],load_data[11:8]}),
        .DOBDO(NLW_memory_reg_2_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_memory_reg_2_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_memory_reg_2_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_memory_reg_2_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(memory_reg_2_ENARDEN_cooolgate_en_sig_2),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_memory_reg_2_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_memory_reg_2_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_memory_reg_2_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT4 #(
    .INIT(16'hff02)) 
    memory_reg_2_ENARDEN_cooolgate_en_gate_3
       (.I0(\state[2]_i_1_n_0 ),
        .I1(\state[1]_i_1_n_0 ),
        .I2(INTERNAL_RST_reg),
        .I3(memory_reg_0_i_1_n_0),
        .O(memory_reg_2_ENARDEN_cooolgate_en_sig_2));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_2_i_1
       (.I0(result[11]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[11]),
        .O(store_data[11]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_2_i_2
       (.I0(result[10]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[10]),
        .O(store_data[10]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_2_i_3
       (.I0(result[9]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[9]),
        .O(store_data[9]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_2_i_4
       (.I0(result[8]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[8]),
        .O(store_data[8]));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENARDEN=NEW" *) 
  (* RTL_RAM_BITS = "131104" *) 
  (* RTL_RAM_NAME = "memory" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "12" *) 
  (* bram_slice_end = "15" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    memory_reg_3
       (.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_memory_reg_3_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[15:12]}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_memory_reg_3_DOADO_UNCONNECTED[31:4],load_data[15:12]}),
        .DOBDO(NLW_memory_reg_3_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_memory_reg_3_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_memory_reg_3_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_memory_reg_3_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(memory_reg_3_ENARDEN_cooolgate_en_sig_3),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_memory_reg_3_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_memory_reg_3_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_memory_reg_3_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT4 #(
    .INIT(16'hff02)) 
    memory_reg_3_ENARDEN_cooolgate_en_gate_5
       (.I0(\state[2]_i_1_n_0 ),
        .I1(\state[1]_i_1_n_0 ),
        .I2(INTERNAL_RST_reg),
        .I3(memory_reg_0_i_1_n_0),
        .O(memory_reg_3_ENARDEN_cooolgate_en_sig_3));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_3_i_1
       (.I0(result[15]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[15]),
        .O(store_data[15]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_3_i_2
       (.I0(result[14]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[14]),
        .O(store_data[14]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_3_i_3
       (.I0(result[13]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[13]),
        .O(store_data[13]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_3_i_4
       (.I0(result[12]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[12]),
        .O(store_data[12]));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENARDEN=NEW" *) 
  (* RTL_RAM_BITS = "131104" *) 
  (* RTL_RAM_NAME = "memory" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "16" *) 
  (* bram_slice_end = "19" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    memory_reg_4
       (.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_memory_reg_4_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[19:16]}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_memory_reg_4_DOADO_UNCONNECTED[31:4],load_data[19:16]}),
        .DOBDO(NLW_memory_reg_4_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_memory_reg_4_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_memory_reg_4_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_memory_reg_4_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(memory_reg_4_ENARDEN_cooolgate_en_sig_4),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_memory_reg_4_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_memory_reg_4_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_memory_reg_4_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT4 #(
    .INIT(16'hff02)) 
    memory_reg_4_ENARDEN_cooolgate_en_gate_7
       (.I0(\state[2]_i_1_n_0 ),
        .I1(\state[1]_i_1_n_0 ),
        .I2(INTERNAL_RST_reg),
        .I3(memory_reg_0_i_1_n_0),
        .O(memory_reg_4_ENARDEN_cooolgate_en_sig_4));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_4_i_1
       (.I0(result[19]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[19]),
        .O(store_data[19]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_4_i_2
       (.I0(result[18]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[18]),
        .O(store_data[18]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_4_i_3
       (.I0(result[17]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[17]),
        .O(store_data[17]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_4_i_4
       (.I0(result[16]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[16]),
        .O(store_data[16]));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENARDEN=NEW" *) 
  (* RTL_RAM_BITS = "131104" *) 
  (* RTL_RAM_NAME = "memory" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "20" *) 
  (* bram_slice_end = "23" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    memory_reg_5
       (.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_memory_reg_5_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[23:20]}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_memory_reg_5_DOADO_UNCONNECTED[31:4],load_data[23:20]}),
        .DOBDO(NLW_memory_reg_5_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_memory_reg_5_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_memory_reg_5_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_memory_reg_5_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(memory_reg_5_ENARDEN_cooolgate_en_sig_5),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_memory_reg_5_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_memory_reg_5_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_memory_reg_5_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT4 #(
    .INIT(16'hff02)) 
    memory_reg_5_ENARDEN_cooolgate_en_gate_9
       (.I0(\state[2]_i_1_n_0 ),
        .I1(\state[1]_i_1_n_0 ),
        .I2(INTERNAL_RST_reg),
        .I3(memory_reg_0_i_1_n_0),
        .O(memory_reg_5_ENARDEN_cooolgate_en_sig_5));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_5_i_1
       (.I0(result[23]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[23]),
        .O(store_data[23]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_5_i_2
       (.I0(result[22]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[22]),
        .O(store_data[22]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_5_i_3
       (.I0(result[21]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[21]),
        .O(store_data[21]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_5_i_4
       (.I0(result[20]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[20]),
        .O(store_data[20]));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENARDEN=NEW" *) 
  (* RTL_RAM_BITS = "131104" *) 
  (* RTL_RAM_NAME = "memory" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "24" *) 
  (* bram_slice_end = "27" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    memory_reg_6
       (.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_memory_reg_6_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[27:24]}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_memory_reg_6_DOADO_UNCONNECTED[31:4],load_data[27:24]}),
        .DOBDO(NLW_memory_reg_6_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_memory_reg_6_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_memory_reg_6_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_memory_reg_6_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(memory_reg_6_ENARDEN_cooolgate_en_sig_6),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_memory_reg_6_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_memory_reg_6_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_memory_reg_6_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT4 #(
    .INIT(16'hff02)) 
    memory_reg_6_ENARDEN_cooolgate_en_gate_11
       (.I0(\state[2]_i_1_n_0 ),
        .I1(\state[1]_i_1_n_0 ),
        .I2(INTERNAL_RST_reg),
        .I3(memory_reg_0_i_1_n_0),
        .O(memory_reg_6_ENARDEN_cooolgate_en_sig_6));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_6_i_1
       (.I0(result[27]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[27]),
        .O(store_data[27]));
  LUT3 #(
    .INIT(8'hB8)) 
    memory_reg_6_i_2
       (.I0(result[26]),
        .I1(operand_b1),
        .I2(register_b[26]),
        .O(store_data[26]));
  LUT3 #(
    .INIT(8'hB8)) 
    memory_reg_6_i_3
       (.I0(result[25]),
        .I1(operand_b1),
        .I2(register_b[25]),
        .O(store_data[25]));
  LUT3 #(
    .INIT(8'hB8)) 
    memory_reg_6_i_4
       (.I0(result[24]),
        .I1(operand_b1),
        .I2(register_b[24]),
        .O(store_data[24]));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENARDEN=NEW" *) 
  (* RTL_RAM_BITS = "131104" *) 
  (* RTL_RAM_NAME = "memory" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "28" *) 
  (* bram_slice_end = "31" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    memory_reg_7
       (.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_memory_reg_7_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[31:28]}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_memory_reg_7_DOADO_UNCONNECTED[31:4],load_data[31:28]}),
        .DOBDO(NLW_memory_reg_7_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_memory_reg_7_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_memory_reg_7_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_memory_reg_7_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(memory_reg_7_ENARDEN_cooolgate_en_sig_7),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_memory_reg_7_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_memory_reg_7_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_memory_reg_7_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT4 #(
    .INIT(16'hff02)) 
    memory_reg_7_ENARDEN_cooolgate_en_gate_13
       (.I0(\state[2]_i_1_n_0 ),
        .I1(\state[1]_i_1_n_0 ),
        .I2(INTERNAL_RST_reg),
        .I3(memory_reg_0_i_1_n_0),
        .O(memory_reg_7_ENARDEN_cooolgate_en_sig_7));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_7_i_1
       (.I0(result[31]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[31]),
        .O(store_data[31]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_7_i_2
       (.I0(result[30]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[30]),
        .O(store_data[30]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    memory_reg_7_i_3
       (.I0(result[29]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[29]),
        .O(store_data[29]));
  LUT3 #(
    .INIT(8'hB8)) 
    memory_reg_7_i_4
       (.I0(result[28]),
        .I1(operand_b1),
        .I2(register_b[28]),
        .O(store_data[28]));
  FDRE \opcode_2_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(opcode[0]),
        .Q(opcode_2[0]),
        .R(1'b0));
  FDRE \opcode_2_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(opcode[1]),
        .Q(opcode_2[1]),
        .R(1'b0));
  FDRE \opcode_2_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(opcode[2]),
        .Q(opcode_2[2]),
        .R(1'b0));
  FDRE \opcode_2_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(opcode[3]),
        .Q(opcode_2[3]),
        .R(1'b0));
  FDRE \opcode_2_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(opcode[4]),
        .Q(opcode_2[4]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h111111111111FFF1)) 
    \program_counter[0]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg_n_0_[0] ),
        .I2(\read_input[31]_i_3_n_0 ),
        .I3(\program_counter[0]_i_2_n_0 ),
        .I4(\program_counter[0]_i_3_n_0 ),
        .I5(\program_counter[0]_i_4_n_0 ),
        .O(sel[0]));
  LUT6 #(
    .INIT(64'h000000000000C5CC)) 
    \program_counter[0]_i_2 
       (.I0(\program_counter_reg_n_0_[0] ),
        .I1(address_b_2[0]),
        .I2(\program_counter[15]_i_8_n_0 ),
        .I3(opcode_2[2]),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[0]_i_3 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(address_b_2[0]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[0]_i_4 
       (.I0(register_a[0]),
        .I1(operand_a1),
        .I2(result[0]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[10]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[12]_i_2_n_6 ),
        .I2(\program_counter[10]_i_2_n_0 ),
        .I3(\program_counter[10]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[10]_i_4_n_0 ),
        .O(sel[10]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[10]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[26]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[10]_i_3 
       (.I0(register_a[10]),
        .I1(operand_a1),
        .I2(result[10]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h1010101011001010)) 
    \program_counter[10]_i_4 
       (.I0(opcode_2[4]),
        .I1(opcode_2[3]),
        .I2(data7[26]),
        .I3(\program_counter_reg[12]_i_2_n_6 ),
        .I4(opcode_2[2]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[11]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[12]_i_2_n_5 ),
        .I2(\program_counter[11]_i_2_n_0 ),
        .I3(\program_counter[11]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[11]_i_4_n_0 ),
        .O(sel[11]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[11]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[27]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[11]_i_3 
       (.I0(register_a[11]),
        .I1(operand_a1),
        .I2(result[11]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h1010101011001010)) 
    \program_counter[11]_i_4 
       (.I0(opcode_2[4]),
        .I1(opcode_2[3]),
        .I2(data7[27]),
        .I3(\program_counter_reg[12]_i_2_n_5 ),
        .I4(opcode_2[2]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[12]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[12]_i_2_n_4 ),
        .I2(\program_counter[12]_i_3_n_0 ),
        .I3(\program_counter[12]_i_4_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[12]_i_5_n_0 ),
        .O(sel[12]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[12]_i_3 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[28]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[12]_i_4 
       (.I0(register_a[12]),
        .I1(operand_a1),
        .I2(result[12]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h1010101011001010)) 
    \program_counter[12]_i_5 
       (.I0(opcode_2[4]),
        .I1(opcode_2[3]),
        .I2(data7[28]),
        .I3(\program_counter_reg[12]_i_2_n_4 ),
        .I4(opcode_2[2]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[12]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h1110FFFF11101110)) 
    \program_counter[13]_i_1 
       (.I0(\program_counter[13]_i_2_n_0 ),
        .I1(\program_counter[13]_i_3_n_0 ),
        .I2(\read_input[31]_i_3_n_0 ),
        .I3(\program_counter[13]_i_4_n_0 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(\program_counter_reg[15]_i_4_n_7 ),
        .O(sel[13]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[13]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[29]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[13]_i_3 
       (.I0(register_a[13]),
        .I1(operand_a1),
        .I2(result[13]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000CACC)) 
    \program_counter[13]_i_4 
       (.I0(\program_counter_reg[15]_i_4_n_7 ),
        .I1(data7[29]),
        .I2(\program_counter[15]_i_8_n_0 ),
        .I3(opcode_2[2]),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[13]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[14]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[15]_i_4_n_6 ),
        .I2(\program_counter[14]_i_2_n_0 ),
        .I3(\program_counter[14]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[14]_i_4_n_0 ),
        .O(sel[14]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[14]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[30]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[14]_i_3 
       (.I0(register_a[14]),
        .I1(operand_a1),
        .I2(result[14]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BA8A)) 
    \program_counter[14]_i_4 
       (.I0(data7[30]),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[15]_i_4_n_6 ),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[14]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h32)) 
    \program_counter[15]_i_1 
       (.I0(\state_reg_n_0_[1] ),
        .I1(\state_reg_n_0_[2] ),
        .I2(\state_reg_n_0_[0] ),
        .O(instruction0));
  LUT2 #(
    .INIT(4'h2)) 
    \program_counter[15]_i_13 
       (.I0(opcode_2[0]),
        .I1(opcode_2[1]),
        .O(\program_counter[15]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'hEFFF)) 
    \program_counter[15]_i_14 
       (.I0(opcode_2[2]),
        .I1(opcode_2[4]),
        .I2(opcode_2[1]),
        .I3(opcode_2[3]),
        .O(\program_counter[15]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \program_counter[15]_i_15 
       (.I0(\state_reg_n_0_[0] ),
        .I1(\state_reg_n_0_[1] ),
        .O(\program_counter[15]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \program_counter[15]_i_16 
       (.I0(\read_input[10]_i_1_n_0 ),
        .I1(\read_input[9]_i_1_n_0 ),
        .I2(\read_input[14]_i_1_n_0 ),
        .I3(\read_input[15]_i_1_n_0 ),
        .I4(\read_input[12]_i_1_n_0 ),
        .I5(\read_input[13]_i_1_n_0 ),
        .O(\program_counter[15]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \program_counter[15]_i_17 
       (.I0(\read_input[24]_i_1_n_0 ),
        .I1(\read_input[23]_i_1_n_0 ),
        .I2(\read_input[28]_i_1_n_0 ),
        .I3(\read_input[29]_i_1_n_0 ),
        .I4(\read_input[25]_i_1_n_0 ),
        .I5(\read_input[26]_i_1_n_0 ),
        .O(\program_counter[15]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000010101)) 
    \program_counter[15]_i_18 
       (.I0(\read_input[2]_i_1_n_0 ),
        .I1(\read_input[1]_i_1_n_0 ),
        .I2(\read_input[8]_i_1_n_0 ),
        .I3(result[4]),
        .I4(operand_a1),
        .I5(register_a[4]),
        .O(\program_counter[15]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \program_counter[15]_i_19 
       (.I0(\read_input[11]_i_1_n_0 ),
        .I1(\read_input[7]_i_1_n_0 ),
        .I2(\read_input[18]_i_1_n_0 ),
        .I3(\read_input[19]_i_1_n_0 ),
        .I4(\read_input[16]_i_1_n_0 ),
        .I5(\read_input[17]_i_1_n_0 ),
        .O(\program_counter[15]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[15]_i_2 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[15]_i_4_n_5 ),
        .I2(\program_counter[15]_i_5_n_0 ),
        .I3(\program_counter[15]_i_6_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[15]_i_7_n_0 ),
        .O(sel[15]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \program_counter[15]_i_20 
       (.I0(\read_input[21]_i_1_n_0 ),
        .I1(\read_input[20]_i_1_n_0 ),
        .I2(\read_input[30]_i_1_n_0 ),
        .I3(\read_input[31]_i_2_n_0 ),
        .I4(\read_input[22]_i_1_n_0 ),
        .I5(\read_input[27]_i_1_n_0 ),
        .O(\program_counter[15]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \program_counter[15]_i_21 
       (.I0(\read_input[3]_i_1_n_0 ),
        .I1(result[0]),
        .I2(operand_a1),
        .I3(register_a[0]),
        .I4(\read_input[6]_i_1_n_0 ),
        .I5(\read_input[5]_i_1_n_0 ),
        .O(\program_counter[15]_i_21_n_0 ));
  LUT5 #(
    .INIT(32'h00000B4B)) 
    \program_counter[15]_i_3 
       (.I0(opcode_2[1]),
        .I1(opcode_2[2]),
        .I2(opcode_2[4]),
        .I3(\program_counter[15]_i_8_n_0 ),
        .I4(\program_counter[15]_i_9_n_0 ),
        .O(\program_counter[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[15]_i_5 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[31]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[15]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[15]_i_6 
       (.I0(register_a[15]),
        .I1(operand_a1),
        .I2(result[15]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BA8A)) 
    \program_counter[15]_i_7 
       (.I0(data7[31]),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[15]_i_4_n_5 ),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[15]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \program_counter[15]_i_8 
       (.I0(\program_counter[15]_i_16_n_0 ),
        .I1(\program_counter[15]_i_17_n_0 ),
        .I2(\program_counter[15]_i_18_n_0 ),
        .I3(\program_counter[15]_i_19_n_0 ),
        .I4(\program_counter[15]_i_20_n_0 ),
        .I5(\program_counter[15]_i_21_n_0 ),
        .O(\program_counter[15]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBFFF3FFF7FFF)) 
    \program_counter[15]_i_9 
       (.I0(opcode_2[2]),
        .I1(\state_reg_n_0_[0] ),
        .I2(\state_reg_n_0_[1] ),
        .I3(opcode_2[0]),
        .I4(opcode_2[1]),
        .I5(opcode_2[3]),
        .O(\program_counter[15]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[1]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[4]_i_2_n_7 ),
        .I2(\program_counter[1]_i_2_n_0 ),
        .I3(\program_counter[1]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[1]_i_4_n_0 ),
        .O(sel[1]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[1]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(address_b_2[1]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[1]_i_3 
       (.I0(register_a[1]),
        .I1(operand_a1),
        .I2(result[1]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BA8A)) 
    \program_counter[1]_i_4 
       (.I0(address_b_2[1]),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[4]_i_2_n_7 ),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[2]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[4]_i_2_n_6 ),
        .I2(\program_counter[2]_i_2_n_0 ),
        .I3(\program_counter[2]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[2]_i_4_n_0 ),
        .O(sel[2]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[2]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(address_b_2[2]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[2]_i_3 
       (.I0(register_a[2]),
        .I1(operand_a1),
        .I2(result[2]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BA8A)) 
    \program_counter[2]_i_4 
       (.I0(address_b_2[2]),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[4]_i_2_n_6 ),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h1110FFFF11101110)) 
    \program_counter[3]_i_1 
       (.I0(\program_counter[3]_i_2_n_0 ),
        .I1(\program_counter[3]_i_3_n_0 ),
        .I2(\read_input[31]_i_3_n_0 ),
        .I3(\program_counter[3]_i_4_n_0 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(\program_counter_reg[4]_i_2_n_5 ),
        .O(sel[3]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[3]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(address_b_2[3]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[3]_i_3 
       (.I0(register_a[3]),
        .I1(operand_a1),
        .I2(result[3]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000CACC)) 
    \program_counter[3]_i_4 
       (.I0(\program_counter_reg[4]_i_2_n_5 ),
        .I1(address_b_2[3]),
        .I2(\program_counter[15]_i_8_n_0 ),
        .I3(opcode_2[2]),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[4]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[4]_i_2_n_4 ),
        .I2(\program_counter[4]_i_3_n_0 ),
        .I3(\program_counter[4]_i_4_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[4]_i_5_n_0 ),
        .O(sel[4]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[4]_i_3 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[20]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[4]_i_4 
       (.I0(register_a[4]),
        .I1(operand_a1),
        .I2(result[4]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000CACC)) 
    \program_counter[4]_i_5 
       (.I0(\program_counter_reg[4]_i_2_n_4 ),
        .I1(data7[20]),
        .I2(\program_counter[15]_i_8_n_0 ),
        .I3(opcode_2[2]),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[5]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[8]_i_2_n_7 ),
        .I2(\program_counter[5]_i_2_n_0 ),
        .I3(\program_counter[5]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[5]_i_4_n_0 ),
        .O(sel[5]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[5]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[21]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[5]_i_3 
       (.I0(register_a[5]),
        .I1(operand_a1),
        .I2(result[5]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BA8A)) 
    \program_counter[5]_i_4 
       (.I0(data7[21]),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[8]_i_2_n_7 ),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[6]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[8]_i_2_n_6 ),
        .I2(\program_counter[6]_i_2_n_0 ),
        .I3(\program_counter[6]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[6]_i_4_n_0 ),
        .O(sel[6]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[6]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[22]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[6]_i_3 
       (.I0(register_a[6]),
        .I1(operand_a1),
        .I2(result[6]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BA8A)) 
    \program_counter[6]_i_4 
       (.I0(data7[22]),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[8]_i_2_n_6 ),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[7]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[8]_i_2_n_5 ),
        .I2(\program_counter[7]_i_2_n_0 ),
        .I3(\program_counter[7]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[7]_i_4_n_0 ),
        .O(sel[7]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[7]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[23]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[7]_i_3 
       (.I0(register_a[7]),
        .I1(operand_a1),
        .I2(result[7]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BA8A)) 
    \program_counter[7]_i_4 
       (.I0(data7[23]),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[8]_i_2_n_5 ),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[8]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[8]_i_2_n_4 ),
        .I2(\program_counter[8]_i_3_n_0 ),
        .I3(\program_counter[8]_i_4_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[8]_i_5_n_0 ),
        .O(sel[8]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[8]_i_3 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[24]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[8]_i_4 
       (.I0(register_a[8]),
        .I1(operand_a1),
        .I2(result[8]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BA8A)) 
    \program_counter[8]_i_5 
       (.I0(data7[24]),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[8]_i_2_n_4 ),
        .I4(opcode_2[4]),
        .I5(opcode_2[3]),
        .O(\program_counter[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h444F444F444F4444)) 
    \program_counter[9]_i_1 
       (.I0(\program_counter[15]_i_3_n_0 ),
        .I1(\program_counter_reg[12]_i_2_n_7 ),
        .I2(\program_counter[9]_i_2_n_0 ),
        .I3(\program_counter[9]_i_3_n_0 ),
        .I4(\read_input[31]_i_3_n_0 ),
        .I5(\program_counter[9]_i_4_n_0 ),
        .O(sel[9]));
  LUT6 #(
    .INIT(64'hAAA2AAAA8AA2AAAA)) 
    \program_counter[9]_i_2 
       (.I0(\program_counter[15]_i_13_n_0 ),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(data7[25]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF1DFFFFFFFF)) 
    \program_counter[9]_i_3 
       (.I0(register_a[9]),
        .I1(operand_a1),
        .I2(result[9]),
        .I3(\program_counter[15]_i_14_n_0 ),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_15_n_0 ),
        .O(\program_counter[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h1010101011001010)) 
    \program_counter[9]_i_4 
       (.I0(opcode_2[4]),
        .I1(opcode_2[3]),
        .I2(data7[25]),
        .I3(\program_counter_reg[12]_i_2_n_7 ),
        .I4(opcode_2[2]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\program_counter[9]_i_4_n_0 ));
  FDRE \program_counter_1_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[0] ),
        .Q(program_counter_1[0]),
        .R(1'b0));
  FDRE \program_counter_1_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[10] ),
        .Q(program_counter_1[10]),
        .R(1'b0));
  FDRE \program_counter_1_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[11] ),
        .Q(program_counter_1[11]),
        .R(1'b0));
  FDRE \program_counter_1_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[12] ),
        .Q(program_counter_1[12]),
        .R(1'b0));
  FDRE \program_counter_1_reg[13] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[13] ),
        .Q(program_counter_1[13]),
        .R(1'b0));
  FDRE \program_counter_1_reg[14] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[14] ),
        .Q(program_counter_1[14]),
        .R(1'b0));
  FDRE \program_counter_1_reg[15] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[15] ),
        .Q(program_counter_1[15]),
        .R(1'b0));
  FDRE \program_counter_1_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[1] ),
        .Q(program_counter_1[1]),
        .R(1'b0));
  FDRE \program_counter_1_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[2] ),
        .Q(program_counter_1[2]),
        .R(1'b0));
  FDRE \program_counter_1_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[3] ),
        .Q(program_counter_1[3]),
        .R(1'b0));
  FDRE \program_counter_1_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[4] ),
        .Q(program_counter_1[4]),
        .R(1'b0));
  FDRE \program_counter_1_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[5] ),
        .Q(program_counter_1[5]),
        .R(1'b0));
  FDRE \program_counter_1_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[6] ),
        .Q(program_counter_1[6]),
        .R(1'b0));
  FDRE \program_counter_1_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[7] ),
        .Q(program_counter_1[7]),
        .R(1'b0));
  FDRE \program_counter_1_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[8] ),
        .Q(program_counter_1[8]),
        .R(1'b0));
  FDRE \program_counter_1_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(\program_counter_reg_n_0_[9] ),
        .Q(program_counter_1[9]),
        .R(1'b0));
  FDRE \program_counter_2_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[0]),
        .Q(program_counter_2[0]),
        .R(1'b0));
  FDRE \program_counter_2_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[10]),
        .Q(program_counter_2[10]),
        .R(1'b0));
  FDRE \program_counter_2_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[11]),
        .Q(program_counter_2[11]),
        .R(1'b0));
  FDRE \program_counter_2_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[12]),
        .Q(program_counter_2[12]),
        .R(1'b0));
  FDRE \program_counter_2_reg[13] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[13]),
        .Q(program_counter_2[13]),
        .R(1'b0));
  FDRE \program_counter_2_reg[14] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[14]),
        .Q(program_counter_2[14]),
        .R(1'b0));
  FDRE \program_counter_2_reg[15] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[15]),
        .Q(program_counter_2[15]),
        .R(1'b0));
  FDRE \program_counter_2_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[1]),
        .Q(program_counter_2[1]),
        .R(1'b0));
  FDRE \program_counter_2_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[2]),
        .Q(program_counter_2[2]),
        .R(1'b0));
  FDRE \program_counter_2_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[3]),
        .Q(program_counter_2[3]),
        .R(1'b0));
  FDRE \program_counter_2_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[4]),
        .Q(program_counter_2[4]),
        .R(1'b0));
  FDRE \program_counter_2_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[5]),
        .Q(program_counter_2[5]),
        .R(1'b0));
  FDRE \program_counter_2_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[6]),
        .Q(program_counter_2[6]),
        .R(1'b0));
  FDRE \program_counter_2_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[7]),
        .Q(program_counter_2[7]),
        .R(1'b0));
  FDRE \program_counter_2_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[8]),
        .Q(program_counter_2[8]),
        .R(1'b0));
  FDRE \program_counter_2_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(opcode_20),
        .D(program_counter_1[9]),
        .Q(program_counter_2[9]),
        .R(1'b0));
  FDRE \program_counter_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[0]),
        .Q(\program_counter_reg_n_0_[0] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[10]),
        .Q(\program_counter_reg_n_0_[10] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[11]),
        .Q(\program_counter_reg_n_0_[11] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[12]),
        .Q(\program_counter_reg_n_0_[12] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \program_counter_reg[12]_i_2 
       (.CI(\program_counter_reg[8]_i_2_n_0 ),
        .CO({\program_counter_reg[12]_i_2_n_0 ,\NLW_program_counter_reg[12]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\program_counter_reg[12]_i_2_n_4 ,\program_counter_reg[12]_i_2_n_5 ,\program_counter_reg[12]_i_2_n_6 ,\program_counter_reg[12]_i_2_n_7 }),
        .S({\program_counter_reg_n_0_[12] ,\program_counter_reg_n_0_[11] ,\program_counter_reg_n_0_[10] ,\program_counter_reg_n_0_[9] }));
  FDRE \program_counter_reg[13] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[13]),
        .Q(\program_counter_reg_n_0_[13] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[14] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[14]),
        .Q(\program_counter_reg_n_0_[14] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[15] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[15]),
        .Q(\program_counter_reg_n_0_[15] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \program_counter_reg[15]_i_4 
       (.CI(\program_counter_reg[12]_i_2_n_0 ),
        .CO(\NLW_program_counter_reg[15]_i_4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_program_counter_reg[15]_i_4_O_UNCONNECTED [3],\program_counter_reg[15]_i_4_n_5 ,\program_counter_reg[15]_i_4_n_6 ,\program_counter_reg[15]_i_4_n_7 }),
        .S({1'b0,\program_counter_reg_n_0_[15] ,\program_counter_reg_n_0_[14] ,\program_counter_reg_n_0_[13] }));
  FDRE \program_counter_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[1]),
        .Q(\program_counter_reg_n_0_[1] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[2]),
        .Q(\program_counter_reg_n_0_[2] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[3]),
        .Q(\program_counter_reg_n_0_[3] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[4]),
        .Q(\program_counter_reg_n_0_[4] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \program_counter_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\program_counter_reg[4]_i_2_n_0 ,\NLW_program_counter_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(\program_counter_reg_n_0_[0] ),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\program_counter_reg[4]_i_2_n_4 ,\program_counter_reg[4]_i_2_n_5 ,\program_counter_reg[4]_i_2_n_6 ,\program_counter_reg[4]_i_2_n_7 }),
        .S({\program_counter_reg_n_0_[4] ,\program_counter_reg_n_0_[3] ,\program_counter_reg_n_0_[2] ,\program_counter_reg_n_0_[1] }));
  FDRE \program_counter_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[5]),
        .Q(\program_counter_reg_n_0_[5] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[6]),
        .Q(\program_counter_reg_n_0_[6] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[7]),
        .Q(\program_counter_reg_n_0_[7] ),
        .R(INTERNAL_RST_reg));
  FDRE \program_counter_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[8]),
        .Q(\program_counter_reg_n_0_[8] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \program_counter_reg[8]_i_2 
       (.CI(\program_counter_reg[4]_i_2_n_0 ),
        .CO({\program_counter_reg[8]_i_2_n_0 ,\NLW_program_counter_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\program_counter_reg[8]_i_2_n_4 ,\program_counter_reg[8]_i_2_n_5 ,\program_counter_reg[8]_i_2_n_6 ,\program_counter_reg[8]_i_2_n_7 }),
        .S({\program_counter_reg_n_0_[8] ,\program_counter_reg_n_0_[7] ,\program_counter_reg_n_0_[6] ,\program_counter_reg_n_0_[5] }));
  FDRE \program_counter_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(instruction0),
        .D(sel[9]),
        .Q(\program_counter_reg_n_0_[9] ),
        .R(INTERNAL_RST_reg));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* POWER_OPTED_CE = "REGCEAREGCE=AUG" *) 
  (* RTL_RAM_BITS = "237568" *) 
  (* RTL_RAM_NAME = "program_counter" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "0" *) 
  (* bram_slice_end = "3" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h18408338258188088F98E78DF8C48BE8AA89688187486785C84683D82B815700),
    .INIT_01(256'hDD8CD8BD8AD89D88D84083A82E81A8008FA8EE8DA8C08B18AA89388287286985),
    .INIT_02(256'h85384583C8268158028F08EE8D289088087A86A85D84D83D82D81D80D8FD8ED8),
    .INIT_03(256'h68C48B288087A86285084E83782E8158008F98E38DE8CD8B18A889088287F864),
    .INIT_04(256'h2381580D8FB8E18D78C78B98A589988E87A86685884483282081380C8FA8E88D),
    .INIT_05(256'h89788287686885984C83182A81D80A8F58D08CA8BE8AA89088A86085684F8318),
    .INIT_06(256'h48FF8E28D08CE8B489088487786885B84983082381480E8FF8E58D18C28B38A6),
    .INIT_07(256'h5C84083982A81E80D8F18E88D08C38BE8AF89988487986385F84083082281F80),
    .INIT_08(256'h8AE89588087486885784983282081C8058FC8E48D48C98BD8A089C8848768658),
    .INIT_09(256'h98348248158038F08E78DE8C98B28A089E88383082081A8018F18E18D08CE8B7),
    .INIT_0A(256'h9188887086985784E83582C81C8058F48E38D78CE8B98A289888087386785E84),
    .INIT_0B(256'h8E98D28C08BC8A589C88487486985D84083C8248168058FC8E08D98CA8BE8AD8),
    .INIT_0C(256'hE8308298148018F58E28D18C08BA8A189188187086E85784E8358208148088F7),
    .INIT_0D(256'h9088A87386E85F84983482981380F8F08E08D28CF8B48AF89288087A86E85E84),
    .INIT_0E(256'h8018F58EB8D48C38B78A789888A87286485584983F82181980A8F08E68D68A08),
    .INIT_0F(256'hC85884E8348238108058F98E48D98C78B28A289A88687086C85884D83E822813),
    .INIT_10(256'hC58B28A989388B87486A85183082A81B8038F58E68DF8C18BA8AD89788187886),
    .INIT_11(256'h8108008F58E58DF8C68B68A989088E87A86785184383D8248178088FC8E28D88),
    .INIT_12(256'h387186885584283981080A8F58EE8D98C88B38A189D88087186D85784983E825),
    .INIT_13(256'hD08C48B18AA89688787386A85684283582981D80B8FF8E78DE8C88B08A489C88),
    .INIT_14(256'h84083382781E8098F48E48D58C38B08AC89588587886785084E8318008F08EA8),
    .INIT_15(256'h589C88087986585E84D8318288108098F58E78D18CC8BE8A589A88C871867858),
    .INIT_16(256'hF78EE8D58C08B48A889788987286085C84583C8248148098FD8E08DC8C48B68A),
    .INIT_17(256'h84183982181A80A8F08E68DF8C38B58A089A88E87A86085A84383282181080E8),
    .INIT_18(256'h8100DE0A0086085A84283782D8138048FB8E78D48C68BE8AC898888872869855),
    .INIT_19(256'h017168C18018618718518618420F01838A20F018B8B20F01858520F018183009),
    .INIT_1A(256'h018D171600F0FF900183171600F0FF900188171600F0FF900182171600F0F000),
    .INIT_1B(256'h0171680000F0FF90018E171600F0FF90018B171600F0FF900188171600F0FF90),
    .INIT_1C(256'hF0FF40018A0F11800BB17165A0F000180B020F0FFE00180011716810C0F0F040),
    .INIT_1D(256'hFF90018E171600F0FF40018A0F11800DB171600F0FF40018A0F11800CB171600),
    .INIT_1E(256'h00018600F0FF400180B0F0FEB00180A0F0FF50018001171618B17161716500F0),
    .INIT_1F(256'h1C070F0FF000180011716C0F80A0F00018118000A00F0FF40018A17168008A0F),
    .INIT_20(256'h90017168B020F0F0900171685020F0F0900171600F0FF90018A1716AA0F00118),
    .INIT_21(256'h0F0F0E00171600F0FF90018D17165A0F001182B80000F0F000017168A020F0F0),
    .INIT_22(256'h686040F0F0500171600F0FF90018117160A0F001183B80000F0F000017168409),
    .INIT_23(256'h871716BA0F001184B80000F0F0000171687040F0F0500171685040F0F0500171),
    .INIT_24(256'h0017168C040F0F0500171680040F0F0500171686040F0F0500171600F0FF9001),
    .INIT_25(256'h18006180071800518006180041800A1800B1800518B17164000BCB80000F0F00),
    .INIT_26(256'h0018000171600F0FF40018006171600F0FF900189171600F0F5C001800C18000),
    .INIT_27(256'h80F0B00518A0F00D181500000F0FF900188171600F0FF4001800C171600F0FF4),
    .INIT_28(256'h0F0900518A0F0020FA1800718180F0D00518A0F00F18180F0C00518A0F00E181),
    .INIT_29(256'hF0700518A0F00B18180F0600518A0F00A18180F0A00518A0F0020FA180081818),
    .INIT_2A(256'h41800718180A0F0020F00418006181CA0FA1800484080F0800518A0F00C18180),
    .INIT_2B(256'h8A0051800083A0F0020F0041800918182A0F0020F0041800818181A0F0020F00),
    .INIT_2C(256'h80F020F0E0F0FFF0018004171618E0051800180F020F0E0F0FFF001800417161),
    .INIT_2D(256'h04171680F020F0041800051800380F020F0E0F0FFF0018004171618400518002),
    .INIT_2E(256'h20F00118C005180E0F0FFF0018004171680F020F000188005180E0F0FFF00180),
    .INIT_2F(256'h000080F84A0F0041811800480F020F002182005180E0F0FFF0018004171680F0),
    .INIT_30(256'h0E800384A0F00F180083A0F00E180060008E010F0FE10018A18A0F00F18A1716),
    .INIT_31(256'h058003850A0F0FE500180011800017168100FEA0F01800FB0048000EBA0F0180),
    .INIT_32(256'h82081080030008A007090F0FE6001800F1800E171600008100585005BA0F0180),
    .INIT_33(256'h218FC80A0F0001800F81A0F001181CA0F0001800F780A0F0001817A0F00E1800),
    .INIT_34(256'h700008EA0F00E18180A0F00018181A0F0011810F82A0F002181180028C8A0F00),
    .INIT_35(256'h1800E1800FF0020F0001800E800100000F0FE400180011800F17160000890018),
    .INIT_36(256'h100008C00030000080F00F1800100008100F80A0F00018118000080F0020F000),
    .INIT_37(256'h165A0F00C00E1800900E400082A0FA1800F6A0F00F1816A0FA1800F2A0F00F18),
    .INIT_38(256'h0E1811716EA0F00D00E1800A00E580F0B00E180E0F0FFF0018A0F00B00E18117),
    .INIT_39(256'hD00E180E0F0FFF0018A0F00D00E1811716E80F0C00E180E0F0FFF0018A0F00C0),
    .INIT_3A(256'h0031800D00E1800800E171618400E1800D00E1800800E171683A0F00F18180F0),
    .INIT_3B(256'hE1800C00E1800700E1716830E0F0FFF0018A0FA0F0020F0E0F0FFF0018A0FA0F),
    .INIT_3C(256'hFFF0018A0FA0F0020F0E0F0FFF0018A0FA0F0031800C00E1800700E171618E00),
    .INIT_3D(256'h18A0FA0F0031800B00E1800600E171618A00E1800B00E1800600E1716830E0F0),
    .INIT_3E(256'hE1800600E1716830020F00318000E830E0F0FFF0018A0FA0F0020F0E0F0FFF00),
    .INIT_3F(256'h0FA0F0020F0E0F0FFF0018A0FA0F0031800B00E1800600E171618800E1800B00),
    .INIT_40(256'h0031800C00E1800700E171618C00E1800C00E1800700E1716830E0F0FFF0018A),
    .INIT_41(256'hE1800D00E1800800E1716830E0F0FFF0018A0FA0F0020F0E0F0FFF0018A0FA0F),
    .INIT_42(256'hFFF0018A0FA0F0020F0E0F0FFF0018A0FA0F0031800D00E1800800E171618200),
    .INIT_43(256'hF70008AA0FA0F00F181181F0A0F0FF7001800F171600008BA0F003181830E0F0),
    .INIT_44(256'h001716100087A0F91800F4A0F00F18000008AA0FA1800FBA0F00F18100008A00),
    .INIT_45(256'h0F00018380008220F01858A0F00018210008220F01811A0F000181800C0F0F04),
    .INIT_46(256'h61AD0008220F0188DA0F00018560008220F018B6A0F000184F0008220F018BFA),
    .INIT_47(256'h000171618260008920F018F6A0F0A0F0FF500180001716181800C0F0F0400171),
    .INIT_48(256'h8920F018D4A0F0A0F0FF500180001716183D0008920F0183DA0F0A0F0FF50018),
    .INIT_49(256'h0840A0F0FF5001800017163020F0FFE00180001716800C0F0F040017161F4000),
    .INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6300),
    .INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    program_counter_reg_rep_0
       (.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_program_counter_reg_rep_0_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_program_counter_reg_rep_0_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_program_counter_reg_rep_0_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_program_counter_reg_rep_0_DOADO_UNCONNECTED[31:4],program_counter_reg_rep_0_n_32,program_counter_reg_rep_0_n_33,program_counter_reg_rep_0_n_34,program_counter_reg_rep_0_n_35}),
        .DOBDO(NLW_program_counter_reg_rep_0_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_program_counter_reg_rep_0_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_program_counter_reg_rep_0_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_program_counter_reg_rep_0_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(program_counter_reg_rep_0_i_1_n_0),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_program_counter_reg_rep_0_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_program_counter_reg_rep_0_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_program_counter_reg_rep_0_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
        .REGCEB(NLW_program_counter_reg_rep_0_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_program_counter_reg_rep_0_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT3 #(
    .INIT(8'h20)) 
    program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_gate_21
       (.I0(instruction0),
        .I1(INTERNAL_RST_reg),
        .I2(instruction0),
        .O(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11));
  LUT4 #(
    .INIT(16'hAFAE)) 
    program_counter_reg_rep_0_i_1
       (.I0(INTERNAL_RST_reg),
        .I1(\state_reg_n_0_[0] ),
        .I2(\state_reg_n_0_[2] ),
        .I3(\state_reg_n_0_[1] ),
        .O(program_counter_reg_rep_0_i_1_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_10
       (.I0(program_counter_reg_rep_0_i_23_n_0),
        .I1(\program_counter[4]_i_4_n_0 ),
        .I2(\program_counter[4]_i_3_n_0 ),
        .I3(\program_counter_reg[4]_i_2_n_4 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_10_n_0));
  LUT6 #(
    .INIT(64'h00000000222222F2)) 
    program_counter_reg_rep_0_i_11
       (.I0(\program_counter_reg[4]_i_2_n_5 ),
        .I1(\program_counter[15]_i_3_n_0 ),
        .I2(program_counter_reg_rep_0_i_24_n_0),
        .I3(\program_counter[3]_i_3_n_0 ),
        .I4(\program_counter[3]_i_2_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_11_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_12
       (.I0(program_counter_reg_rep_0_i_25_n_0),
        .I1(\program_counter[2]_i_3_n_0 ),
        .I2(\program_counter[2]_i_2_n_0 ),
        .I3(\program_counter_reg[4]_i_2_n_6 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_12_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_13
       (.I0(program_counter_reg_rep_0_i_26_n_0),
        .I1(\program_counter[1]_i_3_n_0 ),
        .I2(\program_counter[1]_i_2_n_0 ),
        .I3(\program_counter_reg[4]_i_2_n_7 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_13_n_0));
  LUT6 #(
    .INIT(64'h00000000101010FF)) 
    program_counter_reg_rep_0_i_14
       (.I0(\program_counter[0]_i_4_n_0 ),
        .I1(\program_counter[0]_i_3_n_0 ),
        .I2(program_counter_reg_rep_0_i_27_n_0),
        .I3(\program_counter_reg_n_0_[0] ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_14_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFEFBAAA)) 
    program_counter_reg_rep_0_i_15
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[12]_i_2_n_4 ),
        .I4(data7[28]),
        .I5(memory_reg_0_i_2_n_0),
        .O(program_counter_reg_rep_0_i_15_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFEFBAAA)) 
    program_counter_reg_rep_0_i_16
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[12]_i_2_n_5 ),
        .I4(data7[27]),
        .I5(memory_reg_0_i_2_n_0),
        .O(program_counter_reg_rep_0_i_16_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFEFBAAA)) 
    program_counter_reg_rep_0_i_17
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[12]_i_2_n_6 ),
        .I4(data7[26]),
        .I5(memory_reg_0_i_2_n_0),
        .O(program_counter_reg_rep_0_i_17_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFEFBAAA)) 
    program_counter_reg_rep_0_i_18
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(\program_counter[15]_i_8_n_0 ),
        .I2(opcode_2[2]),
        .I3(\program_counter_reg[12]_i_2_n_7 ),
        .I4(data7[25]),
        .I5(memory_reg_0_i_2_n_0),
        .O(program_counter_reg_rep_0_i_18_n_0));
  LUT6 #(
    .INIT(64'hBBBBBABBAAAABAAA)) 
    program_counter_reg_rep_0_i_19
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(\program_counter_reg[8]_i_2_n_4 ),
        .I3(opcode_2[2]),
        .I4(\program_counter[15]_i_8_n_0 ),
        .I5(data7[24]),
        .O(program_counter_reg_rep_0_i_19_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_2
       (.I0(program_counter_reg_rep_0_i_15_n_0),
        .I1(\program_counter[12]_i_4_n_0 ),
        .I2(\program_counter[12]_i_3_n_0 ),
        .I3(\program_counter_reg[12]_i_2_n_4 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_2_n_0));
  LUT6 #(
    .INIT(64'hBBBBBABBAAAABAAA)) 
    program_counter_reg_rep_0_i_20
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(\program_counter_reg[8]_i_2_n_5 ),
        .I3(opcode_2[2]),
        .I4(\program_counter[15]_i_8_n_0 ),
        .I5(data7[23]),
        .O(program_counter_reg_rep_0_i_20_n_0));
  LUT6 #(
    .INIT(64'hBBBBBABBAAAABAAA)) 
    program_counter_reg_rep_0_i_21
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(\program_counter_reg[8]_i_2_n_6 ),
        .I3(opcode_2[2]),
        .I4(\program_counter[15]_i_8_n_0 ),
        .I5(data7[22]),
        .O(program_counter_reg_rep_0_i_21_n_0));
  LUT6 #(
    .INIT(64'hBBBBBABBAAAABAAA)) 
    program_counter_reg_rep_0_i_22
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(\program_counter_reg[8]_i_2_n_7 ),
        .I3(opcode_2[2]),
        .I4(\program_counter[15]_i_8_n_0 ),
        .I5(data7[21]),
        .O(program_counter_reg_rep_0_i_22_n_0));
  LUT6 #(
    .INIT(64'hBBBBAABABBABAAAA)) 
    program_counter_reg_rep_0_i_23
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(opcode_2[2]),
        .I3(\program_counter[15]_i_8_n_0 ),
        .I4(data7[20]),
        .I5(\program_counter_reg[4]_i_2_n_4 ),
        .O(program_counter_reg_rep_0_i_23_n_0));
  LUT6 #(
    .INIT(64'hBBBBAABABBABAAAA)) 
    program_counter_reg_rep_0_i_24
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(opcode_2[2]),
        .I3(\program_counter[15]_i_8_n_0 ),
        .I4(address_b_2[3]),
        .I5(\program_counter_reg[4]_i_2_n_5 ),
        .O(program_counter_reg_rep_0_i_24_n_0));
  LUT6 #(
    .INIT(64'hBBBBBABBAAAABAAA)) 
    program_counter_reg_rep_0_i_25
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(\program_counter_reg[4]_i_2_n_6 ),
        .I3(opcode_2[2]),
        .I4(\program_counter[15]_i_8_n_0 ),
        .I5(address_b_2[2]),
        .O(program_counter_reg_rep_0_i_25_n_0));
  LUT6 #(
    .INIT(64'hBBBBBABBAAAABAAA)) 
    program_counter_reg_rep_0_i_26
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(\program_counter_reg[4]_i_2_n_7 ),
        .I3(opcode_2[2]),
        .I4(\program_counter[15]_i_8_n_0 ),
        .I5(address_b_2[1]),
        .O(program_counter_reg_rep_0_i_26_n_0));
  LUT6 #(
    .INIT(64'hBBABAAAABBBBAABA)) 
    program_counter_reg_rep_0_i_27
       (.I0(\read_input[31]_i_3_n_0 ),
        .I1(memory_reg_0_i_2_n_0),
        .I2(opcode_2[2]),
        .I3(\program_counter[15]_i_8_n_0 ),
        .I4(address_b_2[0]),
        .I5(\program_counter_reg_n_0_[0] ),
        .O(program_counter_reg_rep_0_i_27_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_3
       (.I0(program_counter_reg_rep_0_i_16_n_0),
        .I1(\program_counter[11]_i_3_n_0 ),
        .I2(\program_counter[11]_i_2_n_0 ),
        .I3(\program_counter_reg[12]_i_2_n_5 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_3_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_4
       (.I0(program_counter_reg_rep_0_i_17_n_0),
        .I1(\program_counter[10]_i_3_n_0 ),
        .I2(\program_counter[10]_i_2_n_0 ),
        .I3(\program_counter_reg[12]_i_2_n_6 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_4_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_5
       (.I0(program_counter_reg_rep_0_i_18_n_0),
        .I1(\program_counter[9]_i_3_n_0 ),
        .I2(\program_counter[9]_i_2_n_0 ),
        .I3(\program_counter_reg[12]_i_2_n_7 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_5_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_6
       (.I0(program_counter_reg_rep_0_i_19_n_0),
        .I1(\program_counter[8]_i_4_n_0 ),
        .I2(\program_counter[8]_i_3_n_0 ),
        .I3(\program_counter_reg[8]_i_2_n_4 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_6_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_7
       (.I0(program_counter_reg_rep_0_i_20_n_0),
        .I1(\program_counter[7]_i_3_n_0 ),
        .I2(\program_counter[7]_i_2_n_0 ),
        .I3(\program_counter_reg[8]_i_2_n_5 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_7_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_8
       (.I0(program_counter_reg_rep_0_i_21_n_0),
        .I1(\program_counter[6]_i_3_n_0 ),
        .I2(\program_counter[6]_i_2_n_0 ),
        .I3(\program_counter_reg[8]_i_2_n_6 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_8_n_0));
  LUT6 #(
    .INIT(64'h000000000202FF02)) 
    program_counter_reg_rep_0_i_9
       (.I0(program_counter_reg_rep_0_i_22_n_0),
        .I1(\program_counter[5]_i_3_n_0 ),
        .I2(\program_counter[5]_i_2_n_0 ),
        .I3(\program_counter_reg[8]_i_2_n_7 ),
        .I4(\program_counter[15]_i_3_n_0 ),
        .I5(INTERNAL_RST_reg),
        .O(program_counter_reg_rep_0_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "237568" *) 
  (* RTL_RAM_NAME = "program_counter" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "4" *) 
  (* bram_slice_end = "7" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h4015015015015014005005004005004005005005004004004004004004004E00),
    .INIT_01(256'h2302302302302302302002002302002001001301001001501401401501401401),
    .INIT_02(256'h0460460460460460450320320330300300300300330330330330330330230230),
    .INIT_03(256'h4054054050050056052052056052056052042046043042046042042047046047),
    .INIT_04(256'h7507507406406406406506406406506406506506506506506506406405405405),
    .INIT_05(256'h0850840850850850840840850840840740700700730700700700700750740750),
    .INIT_06(256'h7096095092092093090094094094094094095095095094084085085085084084),
    .INIT_07(256'hB60B20B20B70B30B20A60A20A20A70A60A60A60A70A60A70A60A70A20A70A60A),
    .INIT_08(256'h0C20C60C20C70C60C60C60C70C20C20C60B60B60B60B60B60B20B20B70B60B60),
    .INIT_09(256'h60E70E70E60E70D20D60D60D60D50D20D20D30D00D00D00D60C60C60C20C20C6),
    .INIT_0A(256'hF60F20F20F20F60F60F70F60F60F60E70E70E60E60E60E50E20E20E70E60E60E),
    .INIT_0B(256'h0060070020020060060060060060060020020070060060F60F20F20F70F30F20),
    .INIT_0C(256'h2022027026026016017010010010016016016012012016012016012017016006),
    .INIT_0D(256'hF20F30F70F60F60F60F70F60F70F60E70E20E70E60E70E60E502002002202202),
    .INIT_0E(256'h0150050040050040040050050050050040040050040040040040F50F50F40F00),
    .INIT_0F(256'h4024024024025025025015015014014015014015015010014014014014014015),
    .INIT_10(256'h3503503403503403403403403003503403402402402402502402402502402502),
    .INIT_11(256'h0500500440440440450440450450440450440450440440450450440340340350),
    .INIT_12(256'h5065064065065065060060056056056056056056054052056056056056056054),
    .INIT_13(256'h7007507407407507507407507407407407407407406406406406506506406406),
    .INIT_14(256'h0920970960960960870870860870820860860860860850820820830800720730),
    .INIT_15(256'h60A60A20A20A30A30A20A30A20A20A2096096096096096096097096096095092),
    .INIT_16(256'hB60B20B60B20B70B60B60B60B70B20B20B60B60B60B60B60A60A20A20A70A60A),
    .INIT_17(256'h0D50D50D40D40D50C50C50C40C50C40C00C00C30C00C00C00C30C30C30C20C20),
    .INIT_18(256'h05001103000E00E40E40E50E40E40E40D40D40D50D40D40D40D50D40D50D40D5),
    .INIT_19(256'h000000F40040240740240D40D00F00060200F00050300F00030D00F00000D003),
    .INIT_1A(256'h0003000000F0FF400008000000F0FF400002000000F0FF400005000000F0F050),
    .INIT_1B(256'h0000000000F0FF400001000000F0FF400009000000F0FF40000D000000F0FF40),
    .INIT_1C(256'hF0FFA000000F40000B20000800F000000E080F0FFB0000000000000030F0F0B0),
    .INIT_1D(256'hFF400007000000F0FFA000000F40000B2000000F0FFA000000F40000B2000000),
    .INIT_1E(256'h00000400F0FFA00000F0F0FFE0000090F0FFD0000000000000200000000800F0),
    .INIT_1F(256'h34020F0FF20000000000040F0000F00000000000E00F0FFA000000000000D00F),
    .INIT_20(256'h300000003060F0F030000000D060F0F0300000000F0FF4000070000500F00000),
    .INIT_21(256'h0F0F0B00000000F0FF4000010000900F000003400000F0F0500000002060F0F0),
    .INIT_22(256'h00D030F0F0400000000F0FF4000020000F00F000003400000F0F050000000D05),
    .INIT_23(256'h0C0000400F000003400000F0F0500000007030F0F0400000002030F0F0400000),
    .INIT_24(256'h0000000F030F0F0400000000030F0F0400000002030F0F0400000000F0FF4000),
    .INIT_25(256'h0000200007000020000D0000D00002000030000D00200001000F4400000F0F05),
    .INIT_26(256'h0000000000000F0FFA0000002000000F0FF40000E000000F0FFE000000F00000),
    .INIT_27(256'h00F0B00F0000F00F004000000F0FF400007000000F0FFA000000F000000F0FFA),
    .INIT_28(256'h0F0B00F0000F0000F10000F00400F0B00F0000F00F00400F0B00F0000F00F004),
    .INIT_29(256'hF0B00F0000F00F00400F0B00F0000F00F00400F0B00F0000F0000F10000F0040),
    .INIT_2A(256'h00000F0040000F0000F0000000F004F00F10000000000F0B00F0000F00F00400),
    .INIT_2B(256'h0100F000000000F0000F0000000F0040000F0000F0000000F0040000F0000F00),
    .INIT_2C(256'h00F000F070F0FFF0000000000000400F0000000F000F070F0FFF000000000000),
    .INIT_2D(256'h00000000F000F00000000F0000000F000F070F0FFF0000000000000300F00000),
    .INIT_2E(256'h00F00000900F00070F0FFF0000000000000F000F00000600F00070F0FFF00000),
    .INIT_2F(256'h000090F0000F0000000000000F000F00000800F00070F0FFF0000000000000F0),
    .INIT_30(256'h0F40000000F00F00000000F00F0000000007080F0FF2000010000F00F0010000),
    .INIT_31(256'h00800000030F0FF900000000000000000000F500F00000F50000000F400F0000),
    .INIT_32(256'h00000000000000300D020F0FFB000000F0000F000000000800000000800F0000),
    .INIT_33(256'h0001F0000F0000000F0000F000000F00F0000000FD0000F000000D00F00F0000),
    .INIT_34(256'hD000C0F00F00F0000000F0000000000F0000000F0000F0000000000003000F00),
    .INIT_35(256'h0000F0000F90000F0000000F000000000F0FF600000050000F00000000020000),
    .INIT_36(256'h4000003000D0000000F00F0000500006AA0F0000F00000000000000F0000F000),
    .INIT_37(256'h00200F00B00F0000B00F00000800F70000FE00F00F006E00F50000FD00F00F00),
    .INIT_38(256'h0F0000000500F00B00F0000B00F200F0B00F00070F0FFF000000F00B00F00000),
    .INIT_39(256'hB00F00070F0FFF000000F00B00F0000000500F0B00F00070F0FFF000000F00B0),
    .INIT_3A(256'h0000000B00F0000B00F000000300F0000B00F0000B00F00000000F00F00400F0),
    .INIT_3B(256'hF0000B00F0000B00F000000070F0FFF000000F00F0000F070F0FFF000000F00F),
    .INIT_3C(256'hFFF000000F00F0000F070F0FFF000000F00F0000000B00F0000B00F000000400),
    .INIT_3D(256'h0000F00F0000000B00F0000B00F000000100F0000B00F0000B00F000000070F0),
    .INIT_3E(256'hF0000B00F0000000000F00000000F00070F0FFF000000F00F0000F070F0FFF00),
    .INIT_3F(256'h0F00F0000F070F0FFF000000F00F0000000B00F0000B00F000000600F0000B00),
    .INIT_40(256'h0000000B00F0000B00F000000900F0000B00F0000B00F000000070F0FFF00000),
    .INIT_41(256'hF0000B00F0000B00F000000070F0FFF000000F00F0000F070F0FFF000000F00F),
    .INIT_42(256'hFFF000000F00F0000F070F0FFF000000F00F0000000B00F0000B00F000000800),
    .INIT_43(256'hF00000900F00F00F006004F050F0FF0000000F000000000F00F00000400070F0),
    .INIT_44(256'h00000000000200F30000F300F00F00300000500F70000F100F00F00600000900),
    .INIT_45(256'h0F00000370000600F0003700F00000360000600F0000600F00000300030F0F0B),
    .INIT_46(256'h003B0000600F0001B00F000003A0000600F000CA00F00000380000600F000580),
    .INIT_47(256'h0000000004F0000500F0007F00F090F0FFD0000000000000400030F0F0B00000),
    .INIT_48(256'h0500F000F400F090F0FFD0000000000000410000500F0006100F090F0FFD0000),
    .INIT_49(256'h003090F0FFD000000000008080F0FFB0000000000000030F0F0B0000000B4000),
    .INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4800),
    .INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    program_counter_reg_rep_1
       (.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_program_counter_reg_rep_1_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_program_counter_reg_rep_1_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_program_counter_reg_rep_1_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_program_counter_reg_rep_1_DOADO_UNCONNECTED[31:4],program_counter_reg_rep_1_n_32,program_counter_reg_rep_1_n_33,program_counter_reg_rep_1_n_34,program_counter_reg_rep_1_n_35}),
        .DOBDO(NLW_program_counter_reg_rep_1_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_program_counter_reg_rep_1_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_program_counter_reg_rep_1_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_program_counter_reg_rep_1_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(program_counter_reg_rep_0_i_1_n_0),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_program_counter_reg_rep_1_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_program_counter_reg_rep_1_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_program_counter_reg_rep_1_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(instruction0),
        .REGCEB(NLW_program_counter_reg_rep_1_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_program_counter_reg_rep_1_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* POWER_OPTED_CE = "REGCEAREGCE=AUG" *) 
  (* RTL_RAM_BITS = "237568" *) 
  (* RTL_RAM_NAME = "program_counter" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "8" *) 
  (* bram_slice_end = "11" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000200),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0100100100100100100100100100100100100100100100000000000000000000),
    .INIT_0C(256'h0010010010010010010010010010010010010010010010010010010010010010),
    .INIT_0D(256'h1001001001001001001001001001001001001001001001001001001001001001),
    .INIT_0E(256'h0200200200200200200200200200200200200200200200200200100100100100),
    .INIT_0F(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_10(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_11(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_12(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_13(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_14(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_15(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_16(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_17(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_18(256'h0200110600020020020020020020020020020020020020020020020020020020),
    .INIT_19(256'h000000100000000000000000000F00020100F00000000F00020000F000000000),
    .INIT_1A(256'h0000000000F0FFD00002000000F0FFD00000000000F0FFD00002000000F0F090),
    .INIT_1B(256'h0000000000F0FFD00001000000F0FFD00000000000F0FFD00000000000F0FFD0),
    .INIT_1C(256'hF0FFD000000F00000010000700F0000007020F0FFD0000000000000000F0F0D0),
    .INIT_1D(256'hFFD00002000000F0FFD000000F0000001000000F0FFD000000F0000001000000),
    .INIT_1E(256'h00000000F0FFD0000010F0FFD0000000F0FF00000000000000100000000700F0),
    .INIT_1F(256'h09000F0FF10000000000090F0000F00000000000700F0FFD000000000000700F),
    .INIT_20(256'h100000000020F0F0100000000020F0F0100000000F0FFD000000000800F00000),
    .INIT_21(256'h0F0F0100000000F0FFD000000000800F000000900000F0F0900000001020F0F0),
    .INIT_22(256'h000020F0F0200000000F0FFD000000000800F000000900000F0F090000000000),
    .INIT_23(256'h020000900F000000900000F0F0900000000020F0F0200000000020F0F0200000),
    .INIT_24(256'h00000001020F0F0200000000020F0F0200000000020F0F0200000000F0FFD000),
    .INIT_25(256'h00000000000000000000000000000100000000000010000000069900000F0F09),
    .INIT_26(256'h0000000000000F0FFD0000000000000F0FFD00001000000F0FF9000000100000),
    .INIT_27(256'h00F0000F0000F00F000000000F0FFD00000000000F0FFD0000001000000F0FFD),
    .INIT_28(256'h0F0000F0000F0000F00000F00000F0000F0000F00F00000F0000F0000F00F000),
    .INIT_29(256'hF0000F0000F00F00000F0000F0000F00F00000F0000F0000F0000F00000F0000),
    .INIT_2A(256'h00000F0000000F0000F0000000F000B00F00000000000F0000F0000F00F00000),
    .INIT_2B(256'h0000F000000000F0000F0000000F0000000F0000F0000000F0000000F0000F00),
    .INIT_2C(256'h00F000F000F0FFB0000000000000000F0000000F000F000F0FFB000000000000),
    .INIT_2D(256'h00000000F000F00000000F0000000F000F000F0FFB0000000000000000F00000),
    .INIT_2E(256'h00F00000000F00000F0FFB0000000000000F000F00000000F00000F0FFB00000),
    .INIT_2F(256'h0000A0F0000F0000000000000F000F00000000F00000F0FFB0000000000000F0),
    .INIT_30(256'h0FC0000000F00F00000000F00F0000000000020F0FFC000000000F00F0000000),
    .INIT_31(256'h00C00000000F0FFC00000000000000000000FC00F00000FC0000000FC00F0000),
    .INIT_32(256'h000000000000000000010F0FFC000000F0000F000000000200000000C00F0000),
    .INIT_33(256'h0000C0000F0000000F0000F000000C00F0000000FC0000F000000C00F00F0000),
    .INIT_34(256'h0000C0F00F00F0000000F0000000000F0000000F0000F00000000000DDD00F00),
    .INIT_35(256'h0000F0000FD0000F0000000F000000000F0FFD00000020000F00000000010000),
    .INIT_36(256'h000000000000000000F00F000020000DDD0F0000F00000000000000F0000F000),
    .INIT_37(256'h00E00F00000F0000000F00000200F00000FD00F00F000D00F00000FD00F00F00),
    .INIT_38(256'h0F0000000E00F00000F0000000FE00F0000F00000F0FFB000000F00000F00000),
    .INIT_39(256'h000F00000F0FFB000000F00000F0000000E00F0000F00000F0FFB000000F0000),
    .INIT_3A(256'h0000000000F0000000F000000000F0000000F0000000F00000000F00F00000F0),
    .INIT_3B(256'hF0000000F0000000F000000000F0FFB000000F00F0000F000F0FFB000000F00F),
    .INIT_3C(256'hFFB000000F00F0000F000F0FFB000000F00F0000000000F0000000F000000000),
    .INIT_3D(256'h0000F00F0000000000F0000000F000000000F0000000F0000000F000000000F0),
    .INIT_3E(256'hF0000000F0000000000F00000000F00000F0FFB000000F00F0000F000F0FFB00),
    .INIT_3F(256'h0F00F0000F000F0FFB000000F00F0000000000F0000000F000000000F0000000),
    .INIT_40(256'h0000000000F0000000F000000000F0000000F0000000F000000000F0FFB00000),
    .INIT_41(256'hF0000000F0000000F000000000F0FFB000000F00F0000F000F0FFB000000F00F),
    .INIT_42(256'hFFB000000F00F0000F000F0FFB000000F00F0000000000F0000000F000000000),
    .INIT_43(256'hF10000000F00F00F0000000000F0FF1000000F000000000100F00000000000F0),
    .INIT_44(256'h00000000000000F00000F100F00F00000000000F00000F100F00F00000000000),
    .INIT_45(256'h0F00000010000200F0002100F00000010000200F0000100F00000000000F0F0D),
    .INIT_46(256'h00110000200F0002100F00000010000200F0002100F00000010000200F000010),
    .INIT_47(256'h000000000010000000F0000100F000F0FF00000000000000000000F0F0D00000),
    .INIT_48(256'h0000F0001200F000F0FF00000000000000020000000F0002200F000F0FF00000),
    .INIT_49(256'h002000F0FF0000000000002020F0FFD0000000000000000F0F0D000000012000),
    .INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2200),
    .INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    program_counter_reg_rep_2
       (.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_program_counter_reg_rep_2_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_program_counter_reg_rep_2_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_program_counter_reg_rep_2_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_program_counter_reg_rep_2_DOADO_UNCONNECTED[31:4],program_counter_reg_rep_2_n_32,program_counter_reg_rep_2_n_33,program_counter_reg_rep_2_n_34,program_counter_reg_rep_2_n_35}),
        .DOBDO(NLW_program_counter_reg_rep_2_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_program_counter_reg_rep_2_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_program_counter_reg_rep_2_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_program_counter_reg_rep_2_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(program_counter_reg_rep_0_i_1_n_0),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_program_counter_reg_rep_2_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_program_counter_reg_rep_2_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_program_counter_reg_rep_2_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
        .REGCEB(NLW_program_counter_reg_rep_2_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_program_counter_reg_rep_2_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "237568" *) 
  (* RTL_RAM_NAME = "program_counter" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "12" *) 
  (* bram_slice_end = "15" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h000000000000000000000000000F00000000F00000000F00000000F000000000),
    .INIT_1A(256'h0000000000F0FF000000000000F0FF000000000000F0FF000000000000F0F000),
    .INIT_1B(256'h0000000000F0FF000000000000F0FF000000000000F0FF000000000000F0FF00),
    .INIT_1C(256'hF0FF0000000F00000000000000F0000000000F0FF00000000000000000F0F000),
    .INIT_1D(256'hFF000000000000F0FF0000000F0000000000000F0FF0000000F0000000000000),
    .INIT_1E(256'h00000000F0FF00000000F0FF00000000F0FF10000000000000000000000000F0),
    .INIT_1F(256'h00000F0FF10000000000000F0000F00000000000000F0FF0000000000000000F),
    .INIT_20(256'h100000000000F0F0100000000000F0F0100000000F0FF0000000000000F00000),
    .INIT_21(256'h0F0F0100000000F0FF0000000000000F000000000000F0F0000000000000F0F0),
    .INIT_22(256'h000000F0F0100000000F0FF0000000000000F000000000000F0F000000000000),
    .INIT_23(256'h000000000F000000000000F0F0000000000000F0F0100000000000F0F0100000),
    .INIT_24(256'h00000000000F0F0100000000000F0F0100000000000F0F0100000000F0FF0000),
    .INIT_25(256'h00000000000000000000000000000000000000000000000000000000000F0F00),
    .INIT_26(256'h0000000000000F0FF00000000000000F0FF000000000000F0FF0000000000000),
    .INIT_27(256'h00F0000F0000F00F000000000F0FF000000000000F0FF00000000000000F0FF0),
    .INIT_28(256'h0F0000F0000F0000F00000F00000F0000F0000F00F00000F0000F0000F00F000),
    .INIT_29(256'hF0000F0000F00F00000F0000F0000F00F00000F0000F0000F0000F00000F0000),
    .INIT_2A(256'h00000F0000000F0000F0000000F000000F00000000000F0000F0000F00F00000),
    .INIT_2B(256'h0000F000000000F0000F0000000F0000000F0000F0000000F0000000F0000F00),
    .INIT_2C(256'h00F000F000F0FF00000000000000000F0000000F000F000F0FF0000000000000),
    .INIT_2D(256'h00000000F000F00000000F0000000F000F000F0FF00000000000000000F00000),
    .INIT_2E(256'h00F00000000F00000F0FF00000000000000F000F00000000F00000F0FF000000),
    .INIT_2F(256'h000000F0000F0000000000000F000F00000000F00000F0FF00000000000000F0),
    .INIT_30(256'h0F00000000F00F00800000F00F0080000000000F0FF0000000000F00F0000000),
    .INIT_31(256'h00000000000F0FF000000000000000000000F000F00000F00000000F000F0000),
    .INIT_32(256'h000000000000000000000F0FF0000000F0000F000000000000000000000F0000),
    .INIT_33(256'h000000000F0000000F0000F000000000F0000000F00000F000000000F00F0080),
    .INIT_34(256'h000000F00F00F0000000F0000000000F0000000F0000F0000000000000000F00),
    .INIT_35(256'h0000F0000F00000F0000000F000000000F0FF000000000000F00000000000000),
    .INIT_36(256'h000000000000000000F00F0000000000000F0000F00000000000000F0000F000),
    .INIT_37(256'h00000F00000F0000000F00000000F00000F000F00F000000F00000F000F00F00),
    .INIT_38(256'h0F0000000000F00000F0000000F000F0000F00000F0FF0000000F00000F00000),
    .INIT_39(256'h000F00000F0FF0000000F00000F0000000000F0000F00000F0FF0000000F0000),
    .INIT_3A(256'h0000000000F0000000F000000000F0000000F0000000F00000000F00F00000F0),
    .INIT_3B(256'hF0000000F0000000F000000000F0FF0000000F00F0000F000F0FF0000000F00F),
    .INIT_3C(256'hFF0000000F00F0000F000F0FF0000000F00F0000000000F0000000F000000000),
    .INIT_3D(256'h0000F00F0000000000F0000000F000000000F0000000F0000000F000000000F0),
    .INIT_3E(256'hF0000000F0000000000F00000000F00000F0FF0000000F00F0000F000F0FF000),
    .INIT_3F(256'h0F00F0000F000F0FF0000000F00F0000000000F0000000F000000000F0000000),
    .INIT_40(256'h0000000000F0000000F000000000F0000000F0000000F000000000F0FF000000),
    .INIT_41(256'hF0000000F0000000F000000000F0FF0000000F00F0000F000F0FF0000000F00F),
    .INIT_42(256'hFF0000000F00F0000F000F0FF0000000F00F0000000000F0000000F000000000),
    .INIT_43(256'hF10000000F00F00F0000001000F0FF1000000F000000000000F00000000000F0),
    .INIT_44(256'h00000000000000F00000F100F00F00000000000F00000F100F00F00000000000),
    .INIT_45(256'h0F00000010000000F0000100F00000010000000F0000100F00000000000F0F00),
    .INIT_46(256'h00110000000F0000100F00000010000000F0000100F00000010000000F000010),
    .INIT_47(256'h000000000010000000F0000100F000F0FF10000000000000000000F0F0000000),
    .INIT_48(256'h0000F0000100F000F0FF10000000000000010000000F0000100F000F0FF10000),
    .INIT_49(256'h000000F0FF1000000000001000F0FF00000000000000000F0F00000000011000),
    .INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1100),
    .INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    program_counter_reg_rep_3
       (.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_program_counter_reg_rep_3_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_program_counter_reg_rep_3_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_program_counter_reg_rep_3_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_program_counter_reg_rep_3_DOADO_UNCONNECTED[31:4],program_counter_reg_rep_3_n_32,program_counter_reg_rep_3_n_33,program_counter_reg_rep_3_n_34,program_counter_reg_rep_3_n_35}),
        .DOBDO(NLW_program_counter_reg_rep_3_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_program_counter_reg_rep_3_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_program_counter_reg_rep_3_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_program_counter_reg_rep_3_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(program_counter_reg_rep_0_i_1_n_0),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_program_counter_reg_rep_3_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_program_counter_reg_rep_3_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_program_counter_reg_rep_3_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(instruction0),
        .REGCEB(NLW_program_counter_reg_rep_3_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_program_counter_reg_rep_3_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* POWER_OPTED_CE = "REGCEAREGCE=AUG" *) 
  (* RTL_RAM_BITS = "237568" *) 
  (* RTL_RAM_NAME = "program_counter" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "16" *) 
  (* bram_slice_end = "19" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0200200200200200200200200200200200200200200200200200200200200300),
    .INIT_01(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_02(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_03(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_04(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_05(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_06(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_07(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_08(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_09(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_0A(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_0B(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_0C(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_0D(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_0E(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_0F(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_10(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_11(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_12(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_13(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_14(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_15(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_16(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_17(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_18(256'h2028030034200200200200200200200200200200200200200200200200200200),
    .INIT_19(256'h4333320020020020020020020833033020833033020833033020833033020280),
    .INIT_1A(256'h4330333333333303433033333333330343303333333333034330333333333303),
    .INIT_1B(256'h4333324033333303433033333333330343303333333333034330333333333303),
    .INIT_1C(256'h3333034338330332880333388332843308203333303433284333324203333303),
    .INIT_1D(256'h3303433033333333330343383303328803333333333034338330332880333333),
    .INIT_1E(256'h2843303333330343320333330343320333330343328433333303333333303333),
    .INIT_1F(256'h0820333330343328433330332483328433033284033333303433033332408833),
    .INIT_20(256'h0343333202033333034333320203333303433333333330343303333883328433),
    .INIT_21(256'h3333303433333333330343303333883328433002403333330343333202033333),
    .INIT_22(256'h3202033333034333333333303433033338833284330024033333303433332020),
    .INIT_23(256'h3033338833284330024033333303433332020333330343333202033333034333),
    .INIT_24(256'h3433332020333330343333202033333034333320203333303433333333330343),
    .INIT_25(256'h3328033280332803328033280332803328033280330333336740002403333330),
    .INIT_26(256'h3433280333333333303433280333333333303433033333333330343328033280),
    .INIT_27(256'h2338828433833284330367433333303433033333333330343328033333333330),
    .INIT_28(256'h3388284338332883303328433023388284338332843302338828433833284330),
    .INIT_29(256'h3882843383328433023388284338332843302338828433833288330332843302),
    .INIT_2A(256'h4332843302483328833284332843308833033284240233882843383328433023),
    .INIT_2B(256'h3828433284248332883328433284330248332883328433284330248332883328),
    .INIT_2C(256'h2338833203333303433284333333828433284233883320333330343328433333),
    .INIT_2D(256'h8433332338833284338284332842338833203333303433284333333828433284),
    .INIT_2E(256'h8332843382843320333330343328433332338833284338284332033333034332),
    .INIT_2F(256'h3674033248332843303328423388332843382843320333330343328433332338),
    .INIT_30(256'h8482842483328433802483328433803674202033333034330338332843303333),
    .INIT_31(256'h8482842420333330343328433284333324284883303328482842428488330332),
    .INIT_32(256'h2402402403674202802033333034332843328433333674202842428488330332),
    .INIT_33(256'h4330024833284332842483328433088332843328402483328433088332843380),
    .INIT_34(256'h0284024833284330248332843302483328433033248332843303328400883328),
    .INIT_35(256'h3328433284828833284332842403674333333034332803328433333674202842),
    .INIT_36(256'h0367420828036743033284332803674000332483328433033284303328833284),
    .INIT_37(256'h3388332882843328828436742083303328488332843308833033284883328433),
    .INIT_38(256'h8433033338833288284332882840233882843320333330343383328828433033),
    .INIT_39(256'h8284332033333034338332882843303333023388284332033333034338332882),
    .INIT_3A(256'h2843328828433288284333333828433288284332882843333248332843302338),
    .INIT_3B(256'h4332882843328828433332420333330343383383328833203333303433833833),
    .INIT_3C(256'h3303433833833288332033333034338338332843328828433288284333333828),
    .INIT_3D(256'h3383383328433288284332882843333338284332882843328828433332420333),
    .INIT_3E(256'h4332882843333242883328433828424203333303433833833288332033333034),
    .INIT_3F(256'h3383328833203333303433833833284332882843328828433333382843328828),
    .INIT_40(256'h2843328828433288284333333828433288284332882843333242033333034338),
    .INIT_41(256'h4332882843328828433332420333330343383383328833203333303433833833),
    .INIT_42(256'h3303433833833288332033333034338338332843328828433288284333333828),
    .INIT_43(256'h4067420833833284330330820333330343328433333674208332843302420333),
    .INIT_44(256'h3433333674208330332848833284330367420833033284883328433036742028),
    .INIT_45(256'h3328433006742083303308833284330067420833033088332843302420333330),
    .INIT_46(256'h3300674208330330883328433006742083303308833284330067420833033088),
    .INIT_47(256'h2843333330067420833033088332033333034332843333330242033333034333),
    .INIT_48(256'h2083303308833203333303433284333333006742083303308833203333303433),
    .INIT_49(256'h4202033333034332843333820333330343328433332420333330343333300674),
    .INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0067),
    .INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    program_counter_reg_rep_4
       (.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_program_counter_reg_rep_4_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_program_counter_reg_rep_4_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_program_counter_reg_rep_4_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_program_counter_reg_rep_4_DOADO_UNCONNECTED[31:4],address_a}),
        .DOBDO(NLW_program_counter_reg_rep_4_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_program_counter_reg_rep_4_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_program_counter_reg_rep_4_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_program_counter_reg_rep_4_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(program_counter_reg_rep_0_i_1_n_0),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_program_counter_reg_rep_4_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_program_counter_reg_rep_4_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_program_counter_reg_rep_4_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
        .REGCEB(NLW_program_counter_reg_rep_4_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_program_counter_reg_rep_4_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* POWER_OPTED_CE = "REGCEAREGCE=AUG" *) 
  (* RTL_RAM_BITS = "237568" *) 
  (* RTL_RAM_NAME = "program_counter" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "20" *) 
  (* bram_slice_end = "23" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h8028028028028028028028028028028028028028028028028028028028028343),
    .INIT_01(256'h2802802802802802802802802802802802802802802802802802802802802802),
    .INIT_02(256'h0280280280280280280280280280280280280280280280280280280280280280),
    .INIT_03(256'h8028028028028028028028028028028028028028028028028028028028028028),
    .INIT_04(256'h2802802802802802802802802802802802802802802802802802802802802802),
    .INIT_05(256'h0280280280280280280280280280280280280280280280280280280280280280),
    .INIT_06(256'h8028028028028028028028028028028028028028028028028028028028028028),
    .INIT_07(256'h2802802802802802802802802802802802802802802802802802802802802802),
    .INIT_08(256'h0280280280280280280280280280280280280280280280280280280280280280),
    .INIT_09(256'h8028028028028028028028028028028028028028028028028028028028028028),
    .INIT_0A(256'h2802802802802802802802802802802802802802802802802802802802802802),
    .INIT_0B(256'h0280280280280280280280280280280280280280280280280280280280280280),
    .INIT_0C(256'h8028028028028028028028028028028028028028028028028028028028028028),
    .INIT_0D(256'h2802802802802802802802802802802802802802802802802802802802802802),
    .INIT_0E(256'h0280280280280280280280280280280280280280280280280280280280280280),
    .INIT_0F(256'h8028028028028028028028028028028028028028028028028028028028028028),
    .INIT_10(256'h2802802802802802802802802802802802802802802802802802802802802802),
    .INIT_11(256'h0280280280280280280280280280280280280280280280280280280280280280),
    .INIT_12(256'h8028028028028028028028028028028028028028028028028028028028028028),
    .INIT_13(256'h2802802802802802802802802802802802802802802802802802802802802802),
    .INIT_14(256'h0280280280280280280280280280280280280280280280280280280280280280),
    .INIT_15(256'h8028028028028028028028028028028028028028028028028028028028028028),
    .INIT_16(256'h2802802802802802802802802802802802802802802802802802802802802802),
    .INIT_17(256'h0280280280280280280280280280280280280280280280280280280280280280),
    .INIT_18(256'h0282830647028028028028028028028028028028028028028028028028028028),
    .INIT_19(256'h7303002802802802802802802823830802823830802823830802823830802828),
    .INIT_1A(256'h7308303036373364730830303637336473083030363733647308303036373364),
    .INIT_1B(256'h7303002836373364730830303637336473083030363733647308303036373364),
    .INIT_1C(256'h3733647308A38308288303008A38283080826373364730828303002826373364),
    .INIT_1D(256'h336473083030363733647308A383082883030363733647308A38308288303036),
    .INIT_1E(256'h8283083637336473082637336473082637336473082830303083030303003637),
    .INIT_1F(256'h808263733647308283030083028A3828308308280363733647308303002808A3),
    .INIT_20(256'h647303002826373364730300282637336473030363733647308303008A382830),
    .INIT_21(256'h637336473030363733647308303008A382830800283637336473030028263733),
    .INIT_22(256'h00282637336473030363733647308303008A3828308002836373364730300282),
    .INIT_23(256'h08303008A3828308002836373364730300282637336473030028263733647303),
    .INIT_24(256'h4730300282637336473030028263733647303002826373364730303637336473),
    .INIT_25(256'h3082830828308283082830828308283082830828308303030430000283637336),
    .INIT_26(256'h4730828303036373364730828303036373364730830303637336473082830828),
    .INIT_27(256'h08328828308A3828308304336373364730830303637336473082830303637336),
    .INIT_28(256'h8328828308A38282383082830808328828308A382830808328828308A3828308),
    .INIT_29(256'h328828308A382830808328828308A382830808328828308A3828238308283080),
    .INIT_2A(256'h830828308028A3828238283082830808A383082802808328828308A382830808),
    .INIT_2B(256'h0882830828028A38282382830828308028A38282382830828308028A38282382),
    .INIT_2C(256'h0832823826373364730828303030882830828083282382637336473082830303),
    .INIT_2D(256'h2830300832823828308828308280832823826373364730828303030882830828),
    .INIT_2E(256'h8238283088283082637336473082830300832823828308828308263733647308),
    .INIT_2F(256'h3043083028A38283083082808328238283088283082637336473082830300832),
    .INIT_30(256'h280828028A38283088028A382830883043028263733647308308A38283083030),
    .INIT_31(256'h280828028263733647308283082830300282808A383082808280282808A38308),
    .INIT_32(256'h0280280283043028288263733647308283082830303043028280282808A38308),
    .INIT_33(256'h83080028A382830828028A382830808A3828308280028A382830808A38283088),
    .INIT_34(256'h28280028A3828308028A3828308028A382830883028A3828308308280008A382),
    .INIT_35(256'h3082830828082823828308280283043363733647308283082830303043028280),
    .INIT_36(256'h830430288283043300382830828304300083028A382830830828300382823828),
    .INIT_37(256'h3008A3828828308288283043028A383082808A382830808A383082808A382830),
    .INIT_38(256'h28308303008A382882830828828008328828308263733647308A382882830830),
    .INIT_39(256'h8828308263733647308A38288283083030008328828308263733647308A38288),
    .INIT_3A(256'h8283082882830828828303030882830828828308288283030028A38283080832),
    .INIT_3B(256'h830828828308288283030028263733647308A38A3828238263733647308A38A3),
    .INIT_3C(256'h33647308A38A3828238263733647308A38A38283082882830828828303030882),
    .INIT_3D(256'h308A38A382830828828308288283030308828308288283082882830300282637),
    .INIT_3E(256'h83082882830300282823828308828028263733647308A38A3828238263733647),
    .INIT_3F(256'hA38A3828238263733647308A38A3828308288283082882830303088283082882),
    .INIT_40(256'h8283082882830828828303030882830828828308288283030028263733647308),
    .INIT_41(256'h830828828308288283030028263733647308A38A3828238263733647308A38A3),
    .INIT_42(256'h33647308A38A3828238263733647308A38A38283082882830828828303030882),
    .INIT_43(256'h80043028A38A3828308308082637336473082830303043028A38283080282637),
    .INIT_44(256'h4730303043028A383082808A38283083043028A383082808A382830830430282),
    .INIT_45(256'hA3828308004302823830808A3828308004302823830808A38283080282637336),
    .INIT_46(256'h030004302823830808A3828308004302823830808A3828308004302823830808),
    .INIT_47(256'h8283030308004302823830808A38263733647308283030308028263733647303),
    .INIT_48(256'h02823830808A38263733647308283030308004302823830808A3826373364730),
    .INIT_49(256'h3028263733647308283030082637336473082830300282637336473030300043),
    .INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0004),
    .INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    program_counter_reg_rep_5
       (.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_program_counter_reg_rep_5_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_program_counter_reg_rep_5_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_program_counter_reg_rep_5_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_program_counter_reg_rep_5_DOADO_UNCONNECTED[31:4],address_z}),
        .DOBDO(NLW_program_counter_reg_rep_5_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_program_counter_reg_rep_5_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_program_counter_reg_rep_5_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_program_counter_reg_rep_5_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(program_counter_reg_rep_0_i_1_n_0),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_program_counter_reg_rep_5_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_program_counter_reg_rep_5_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_program_counter_reg_rep_5_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
        .REGCEB(NLW_program_counter_reg_rep_5_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_program_counter_reg_rep_5_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* POWER_OPTED_CE = "REGCEAREGCE=AUG" *) 
  (* RTL_RAM_BITS = "237568" *) 
  (* RTL_RAM_NAME = "program_counter" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "24" *) 
  (* bram_slice_end = "27" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0200200200200200200200200200200200200200200200200200200200200100),
    .INIT_01(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_02(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_03(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_04(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_05(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_06(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_07(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_08(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_09(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_0A(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_0B(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_0C(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_0D(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_0E(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_0F(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_10(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_11(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_12(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_13(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_14(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_15(256'h0200200200200200200200200200200200200200200200200200200200200200),
    .INIT_16(256'h0020020020020020020020020020020020020020020020020020020020020020),
    .INIT_17(256'h2002002002002002002002002002002002002002002002002002002002002002),
    .INIT_18(256'h2051014311200200200200200200200200200200200200200200200200200200),
    .INIT_19(256'h1121220020020020020020020651012020651012020651012020651012020510),
    .INIT_1A(256'h1120121215151131112012121515113111201212151511311120121215151131),
    .INIT_1B(256'h1121221015151131112012121515113111201212151511311120121215151131),
    .INIT_1C(256'h1511311126510125110121278515111207505151131112511121221505151131),
    .INIT_1D(256'h1131112012121515113111265101251101212151511311126510125110121215),
    .INIT_1E(256'h5111201515113111250515113111250515113111251112121201212121291515),
    .INIT_1F(256'h0750515113111251112129512165151112012511915151131112012122107851),
    .INIT_20(256'h3111212205051511311121220505151131112121515113111201212785151112),
    .INIT_21(256'h5151131112121515113111201212785151112092101515113111212205051511),
    .INIT_22(256'h2205051511311121215151131112012127851511120921015151131112122050),
    .INIT_23(256'h2012127851511120921015151131112122050515113111212205051511311121),
    .INIT_24(256'h1112122050515113111212205051511311121220505151131112121515113111),
    .INIT_25(256'h125101251012510125101251012510125101251012012121A119992101515113),
    .INIT_26(256'h1112510121215151131112510121215151131112012121515113111251012510),
    .INIT_27(256'h2511151112B515111201A1115151131112012121515113111251012121515113),
    .INIT_28(256'h511151112B51516510125111202511151112B515111202511151112B51511120),
    .INIT_29(256'h11151112B515111202511151112B515111202511151112B51516510125111202),
    .INIT_2A(256'h11251112021B5151651511125111207C510125112102511151112B5151112025),
    .INIT_2B(256'h215111251121B51516515111251112021B51516515111251112021B515165151),
    .INIT_2C(256'h2511651505151131112511121212151112511251165150515113111251112121),
    .INIT_2D(256'h1112122511651511121511125112511651505151131112511121212151112511),
    .INIT_2E(256'h6515111215111250515113111251112122511651511121511125051511311125),
    .INIT_2F(256'h1A11951216515111201251125116515111215111250515113111251112122511),
    .INIT_30(256'h11751121E5151112D021E5151112D01A11205051511311120126515111201212),
    .INIT_31(256'h11751121505151131112511125111212215119B510125117511215119B510125),
    .INIT_32(256'h2102102101A11205105051511311125111251112121A1120511215119B510125),
    .INIT_33(256'h1120921B515111251121F51511120705151112511921F515111207E5151112D0),
    .INIT_34(256'h0511921151511120211515111202115151112051216515111201251199785151),
    .INIT_35(256'h1251112511751651511125112101A11151511311125101251112121A11205112),
    .INIT_36(256'h01A112035101A111251511125101A11999512165151112012511125151651511),
    .INIT_37(256'h127851511511125115111A112045101251174515111205451012511745151112),
    .INIT_38(256'h1112012127851511511125115119251115111250515113111265151151112012),
    .INIT_39(256'h1511125051511311126515115111201212925111511125051511311126515115),
    .INIT_3A(256'h511125115111251151112121215111251151112511511121221B515111202511),
    .INIT_3B(256'h11251151112511511121221505151131112651B5151651505151131112B51651),
    .INIT_3C(256'h1131112651B5151651505151131112B516515111251151112511511121212151),
    .INIT_3D(256'h12B5165151112511511125115111212121511125115111251151112122150515),
    .INIT_3E(256'h1125115111212215165151112151121505151131112651B51516515051511311),
    .INIT_3F(256'h51B5151651505151131112B51651511125115111251151112121215111251151),
    .INIT_40(256'h5111251151112511511121212151112511511125115111212215051511311126),
    .INIT_41(256'h11251151112511511121221505151131112651B5151651505151131112B51651),
    .INIT_42(256'h1131112651B5151651505151131112B516515111251151112511511121212151),
    .INIT_43(256'h19A1120651B51511120120750515113111251112121A11206515111202150515),
    .INIT_44(256'h1112121A112045101251174515111201A112045101251174515111201A112051),
    .INIT_45(256'h515111209A1120651012078515111209A1120651012078515111202150515113),
    .INIT_46(256'h2199A1120651012078515111209A1120651012078515111209A1120651012078),
    .INIT_47(256'h51112121209A1120651012078515051511311125111212120215051511311121),
    .INIT_48(256'h206510120785150515113111251112121209A112065101207851505151131112),
    .INIT_49(256'h1205051511311125111212750515113111251112122150515113111212199A11),
    .INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99A1),
    .INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(4),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(4),
    .WRITE_WIDTH_B(0)) 
    program_counter_reg_rep_6
       (.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(NLW_program_counter_reg_rep_6_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_program_counter_reg_rep_6_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DBITERR(NLW_program_counter_reg_rep_6_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
        .DOADO({NLW_program_counter_reg_rep_6_DOADO_UNCONNECTED[31:4],opcode[3:0]}),
        .DOBDO(NLW_program_counter_reg_rep_6_DOBDO_UNCONNECTED[31:0]),
        .DOPADOP(NLW_program_counter_reg_rep_6_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_program_counter_reg_rep_6_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_program_counter_reg_rep_6_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(program_counter_reg_rep_0_i_1_n_0),
        .ENBWREN(1'b0),
        .INJECTDBITERR(NLW_program_counter_reg_rep_6_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_program_counter_reg_rep_6_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_program_counter_reg_rep_6_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
        .REGCEB(NLW_program_counter_reg_rep_6_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_program_counter_reg_rep_6_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* POWER_OPTED_CE = "REGCEAREGCE=AUG" *) 
  (* RTL_RAM_BITS = "237568" *) 
  (* RTL_RAM_NAME = "program_counter" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "8191" *) 
  (* bram_slice_begin = "28" *) 
  (* bram_slice_end = "31" *) 
  RAMB18E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000004000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000010000040000100000000000000000),
    .INIT_1B(256'h0000000000000400004000140000400000010000400000000000000000100000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000040000400000010000100000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00),
    .INIT_26(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_27(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_28(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_29(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_2A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_2B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_2C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_2D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_2E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_2F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_30(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_31(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_32(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_33(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_34(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_35(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_36(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_37(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_38(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_39(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_3A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_3B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_3C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_3D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_3E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_3F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
    .INIT_A(18'h00000),
    .INIT_B(18'h00000),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(2),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(18'h00000),
    .SRVAL_B(18'h00000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(2),
    .WRITE_WIDTH_B(0)) 
    program_counter_reg_rep_7
       (.ADDRARDADDR({program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(1'b0),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1}),
        .DOADO({NLW_program_counter_reg_rep_7_DOADO_UNCONNECTED[15:1],opcode[4]}),
        .DOBDO(NLW_program_counter_reg_rep_7_DOBDO_UNCONNECTED[15:0]),
        .DOPADOP(NLW_program_counter_reg_rep_7_DOPADOP_UNCONNECTED[1:0]),
        .DOPBDOP(NLW_program_counter_reg_rep_7_DOPBDOP_UNCONNECTED[1:0]),
        .ENARDEN(program_counter_reg_rep_0_i_1_n_0),
        .ENBWREN(1'b0),
        .REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
        .REGCEB(NLW_program_counter_reg_rep_7_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .WEA({1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0}));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[0]_i_1 
       (.I0(result[0]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[0]),
        .O(\read_input[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[10]_i_1 
       (.I0(result[10]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[10]),
        .O(\read_input[10]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[11]_i_1 
       (.I0(result[11]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[11]),
        .O(\read_input[11]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[12]_i_1 
       (.I0(result[12]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[12]),
        .O(\read_input[12]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[13]_i_1 
       (.I0(result[13]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[13]),
        .O(\read_input[13]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[14]_i_1 
       (.I0(result[14]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[14]),
        .O(\read_input[14]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[15]_i_1 
       (.I0(result[15]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[15]),
        .O(\read_input[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[16]_i_1 
       (.I0(result[16]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[16]),
        .O(\read_input[16]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[17]_i_1 
       (.I0(result[17]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[17]),
        .O(\read_input[17]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[18]_i_1 
       (.I0(result[18]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[18]),
        .O(\read_input[18]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[19]_i_1 
       (.I0(result[19]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[19]),
        .O(\read_input[19]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[1]_i_1 
       (.I0(result[1]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[1]),
        .O(\read_input[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[20]_i_1 
       (.I0(result[20]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[20]),
        .O(\read_input[20]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[21]_i_1 
       (.I0(result[21]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[21]),
        .O(\read_input[21]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[22]_i_1 
       (.I0(result[22]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[22]),
        .O(\read_input[22]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[23]_i_1 
       (.I0(result[23]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[23]),
        .O(\read_input[23]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[24]_i_1 
       (.I0(result[24]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[24]),
        .O(\read_input[24]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[25]_i_1 
       (.I0(result[25]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[25]),
        .O(\read_input[25]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[26]_i_1 
       (.I0(result[26]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[26]),
        .O(\read_input[26]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[27]_i_1 
       (.I0(result[27]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[27]),
        .O(\read_input[27]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[28]_i_1 
       (.I0(result[28]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[28]),
        .O(\read_input[28]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[29]_i_1 
       (.I0(result[29]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[29]),
        .O(\read_input[29]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[2]_i_1 
       (.I0(result[2]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[2]),
        .O(\read_input[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[30]_i_1 
       (.I0(result[30]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[30]),
        .O(\read_input[30]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \read_input[31]_i_1 
       (.I0(opcode_2[4]),
        .I1(opcode_20),
        .I2(\state_reg_n_0_[0] ),
        .I3(\read_input[31]_i_3_n_0 ),
        .I4(opcode_2[2]),
        .I5(opcode_2[3]),
        .O(\read_input[31]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[31]_i_2 
       (.I0(result[31]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[31]),
        .O(\read_input[31]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \read_input[31]_i_3 
       (.I0(opcode_2[0]),
        .I1(opcode_2[1]),
        .O(\read_input[31]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \read_input[31]_i_4 
       (.I0(address_a_2[2]),
        .I1(address_z_3[2]),
        .I2(address_a_2[1]),
        .I3(address_z_3[1]),
        .O(\read_input[31]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \read_input[31]_i_5 
       (.I0(address_a_2[0]),
        .I1(address_z_3[0]),
        .I2(address_a_2[3]),
        .I3(address_z_3[3]),
        .O(\read_input[31]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[3]_i_1 
       (.I0(result[3]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[3]),
        .O(\read_input[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[4]_i_1 
       (.I0(result[4]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[4]),
        .O(\read_input[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[5]_i_1 
       (.I0(result[5]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[5]),
        .O(\read_input[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[6]_i_1 
       (.I0(result[6]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[6]),
        .O(\read_input[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[7]_i_1 
       (.I0(result[7]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[7]),
        .O(\read_input[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[8]_i_1 
       (.I0(result[8]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[8]),
        .O(\read_input[8]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \read_input[9]_i_1 
       (.I0(result[9]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[9]),
        .O(\read_input[9]_i_1_n_0 ));
  FDRE \read_input_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[0]_i_1_n_0 ),
        .Q(read_input[0]),
        .R(1'b0));
  FDRE \read_input_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[10]_i_1_n_0 ),
        .Q(read_input[10]),
        .R(1'b0));
  FDRE \read_input_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[11]_i_1_n_0 ),
        .Q(read_input[11]),
        .R(1'b0));
  FDRE \read_input_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[12]_i_1_n_0 ),
        .Q(read_input[12]),
        .R(1'b0));
  FDRE \read_input_reg[13] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[13]_i_1_n_0 ),
        .Q(read_input[13]),
        .R(1'b0));
  FDRE \read_input_reg[14] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[14]_i_1_n_0 ),
        .Q(read_input[14]),
        .R(1'b0));
  FDRE \read_input_reg[15] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[15]_i_1_n_0 ),
        .Q(read_input[15]),
        .R(1'b0));
  FDRE \read_input_reg[16] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[16]_i_1_n_0 ),
        .Q(read_input[16]),
        .R(1'b0));
  FDRE \read_input_reg[17] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[17]_i_1_n_0 ),
        .Q(read_input[17]),
        .R(1'b0));
  FDRE \read_input_reg[18] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[18]_i_1_n_0 ),
        .Q(read_input[18]),
        .R(1'b0));
  FDRE \read_input_reg[19] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[19]_i_1_n_0 ),
        .Q(read_input[19]),
        .R(1'b0));
  FDRE \read_input_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[1]_i_1_n_0 ),
        .Q(read_input[1]),
        .R(1'b0));
  FDRE \read_input_reg[20] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[20]_i_1_n_0 ),
        .Q(read_input[20]),
        .R(1'b0));
  FDRE \read_input_reg[21] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[21]_i_1_n_0 ),
        .Q(read_input[21]),
        .R(1'b0));
  FDRE \read_input_reg[22] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[22]_i_1_n_0 ),
        .Q(read_input[22]),
        .R(1'b0));
  FDRE \read_input_reg[23] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[23]_i_1_n_0 ),
        .Q(read_input[23]),
        .R(1'b0));
  FDRE \read_input_reg[24] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[24]_i_1_n_0 ),
        .Q(read_input[24]),
        .R(1'b0));
  FDRE \read_input_reg[25] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[25]_i_1_n_0 ),
        .Q(read_input[25]),
        .R(1'b0));
  FDRE \read_input_reg[26] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[26]_i_1_n_0 ),
        .Q(read_input[26]),
        .R(1'b0));
  FDRE \read_input_reg[27] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[27]_i_1_n_0 ),
        .Q(read_input[27]),
        .R(1'b0));
  FDRE \read_input_reg[28] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[28]_i_1_n_0 ),
        .Q(read_input[28]),
        .R(1'b0));
  FDRE \read_input_reg[29] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[29]_i_1_n_0 ),
        .Q(read_input[29]),
        .R(1'b0));
  FDRE \read_input_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[2]_i_1_n_0 ),
        .Q(read_input[2]),
        .R(1'b0));
  FDRE \read_input_reg[30] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[30]_i_1_n_0 ),
        .Q(read_input[30]),
        .R(1'b0));
  FDRE \read_input_reg[31] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[31]_i_2_n_0 ),
        .Q(read_input[31]),
        .R(1'b0));
  FDRE \read_input_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[3]_i_1_n_0 ),
        .Q(read_input[3]),
        .R(1'b0));
  FDRE \read_input_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[4]_i_1_n_0 ),
        .Q(read_input[4]),
        .R(1'b0));
  FDRE \read_input_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[5]_i_1_n_0 ),
        .Q(read_input[5]),
        .R(1'b0));
  FDRE \read_input_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[6]_i_1_n_0 ),
        .Q(read_input[6]),
        .R(1'b0));
  FDRE \read_input_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[7]_i_1_n_0 ),
        .Q(read_input[7]),
        .R(1'b0));
  FDRE \read_input_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[8]_i_1_n_0 ),
        .Q(read_input[8]),
        .R(1'b0));
  FDRE \read_input_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\read_input[31]_i_1_n_0 ),
        .D(\read_input[9]_i_1_n_0 ),
        .Q(read_input[9]),
        .R(1'b0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_UNIQ_BASE_ registers_reg_r1_0_15_0_5
       (.ADDRA({1'b0,address_b_2}),
        .ADDRB({1'b0,address_b_2}),
        .ADDRC({1'b0,address_b_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[1:0]),
        .DIB(result[3:2]),
        .DIC(result[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(register_b[1:0]),
        .DOB(register_b[3:2]),
        .DOC(register_b[5:4]),
        .DOD(NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD5 registers_reg_r1_0_15_12_17
       (.ADDRA({1'b0,address_b_2}),
        .ADDRB({1'b0,address_b_2}),
        .ADDRC({1'b0,address_b_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[13:12]),
        .DIB(result[15:14]),
        .DIC(result[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(register_b[13:12]),
        .DOB(register_b[15:14]),
        .DOC(register_b[17:16]),
        .DOD(NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD6 registers_reg_r1_0_15_18_23
       (.ADDRA({1'b0,address_b_2}),
        .ADDRB({1'b0,address_b_2}),
        .ADDRC({1'b0,address_b_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[19:18]),
        .DIB(result[21:20]),
        .DIC(result[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(register_b[19:18]),
        .DOB(register_b[21:20]),
        .DOC(register_b[23:22]),
        .DOD(NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD7 registers_reg_r1_0_15_24_29
       (.ADDRA({1'b0,address_b_2}),
        .ADDRB({1'b0,address_b_2}),
        .ADDRC({1'b0,address_b_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[25:24]),
        .DIB(result[27:26]),
        .DIC(result[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(register_b[25:24]),
        .DOB(register_b[27:26]),
        .DOC(register_b[29:28]),
        .DOD(NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD8 registers_reg_r1_0_15_30_31
       (.ADDRA({1'b0,address_b_2}),
        .ADDRB({1'b0,address_b_2}),
        .ADDRC({1'b0,address_b_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[31:30]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(register_b[31:30]),
        .DOB(NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD4 registers_reg_r1_0_15_6_11
       (.ADDRA({1'b0,address_b_2}),
        .ADDRB({1'b0,address_b_2}),
        .ADDRC({1'b0,address_b_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[7:6]),
        .DIB(result[9:8]),
        .DIC(result[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(register_b[7:6]),
        .DOB(register_b[9:8]),
        .DOC(register_b[11:10]),
        .DOD(NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD9 registers_reg_r2_0_15_0_5
       (.ADDRA({1'b0,address_a_2}),
        .ADDRB({1'b0,address_a_2}),
        .ADDRC({1'b0,address_a_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[1:0]),
        .DIB(result[3:2]),
        .DIC(result[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(register_a[1:0]),
        .DOB(register_a[3:2]),
        .DOC(register_a[5:4]),
        .DOD(NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD11 registers_reg_r2_0_15_12_17
       (.ADDRA({1'b0,address_a_2}),
        .ADDRB({1'b0,address_a_2}),
        .ADDRC({1'b0,address_a_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[13:12]),
        .DIB(result[15:14]),
        .DIC(result[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(register_a[13:12]),
        .DOB(register_a[15:14]),
        .DOC(register_a[17:16]),
        .DOD(NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD12 registers_reg_r2_0_15_18_23
       (.ADDRA({1'b0,address_a_2}),
        .ADDRB({1'b0,address_a_2}),
        .ADDRC({1'b0,address_a_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[19:18]),
        .DIB(result[21:20]),
        .DIC(result[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(register_a[19:18]),
        .DOB(register_a[21:20]),
        .DOC(register_a[23:22]),
        .DOD(NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD13 registers_reg_r2_0_15_24_29
       (.ADDRA({1'b0,address_a_2}),
        .ADDRB({1'b0,address_a_2}),
        .ADDRC({1'b0,address_a_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[25:24]),
        .DIB(result[27:26]),
        .DIC(result[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(register_a[25:24]),
        .DOB(register_a[27:26]),
        .DOC(register_a[29:28]),
        .DOD(NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD14 registers_reg_r2_0_15_30_31
       (.ADDRA({1'b0,address_a_2}),
        .ADDRB({1'b0,address_a_2}),
        .ADDRC({1'b0,address_a_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[31:30]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(register_a[31:30]),
        .DOB(NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  (* INIT_A = "64'h0000000000000000" *) 
  (* INIT_B = "64'h0000000000000000" *) 
  (* INIT_C = "64'h0000000000000000" *) 
  (* INIT_D = "64'h0000000000000000" *) 
  RAM32M_HD10 registers_reg_r2_0_15_6_11
       (.ADDRA({1'b0,address_a_2}),
        .ADDRB({1'b0,address_a_2}),
        .ADDRC({1'b0,address_a_2}),
        .ADDRD({1'b0,address_z_3}),
        .DIA(result[7:6]),
        .DIB(result[9:8]),
        .DIC(result[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(register_a[7:6]),
        .DOB(register_a[9:8]),
        .DOC(register_a[11:10]),
        .DOD(NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(ETH_CLK_OBUF),
        .WE(write_enable_reg_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF350000)) 
    \result[0]_i_1 
       (.I0(\result[0]_i_2_n_0 ),
        .I1(\result[0]_i_3_n_0 ),
        .I2(opcode_2[0]),
        .I3(\result[0]_i_4_n_0 ),
        .I4(\state_reg_n_0_[0] ),
        .I5(\result[0]_i_5_n_0 ),
        .O(\result[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h444444D4D4D444D4)) 
    \result[0]_i_100 
       (.I0(store_data[7]),
        .I1(\read_input[7]_i_1_n_0 ),
        .I2(\read_input[6]_i_1_n_0 ),
        .I3(register_b[6]),
        .I4(operand_b1),
        .I5(result[6]),
        .O(\result[0]_i_100_n_0 ));
  LUT6 #(
    .INIT(64'h47004700FF474700)) 
    \result[0]_i_101 
       (.I0(result[5]),
        .I1(operand_b1),
        .I2(register_b[5]),
        .I3(\read_input[5]_i_1_n_0 ),
        .I4(\read_input[4]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[0]_i_101_n_0 ));
  LUT6 #(
    .INIT(64'h5404FFFF00005404)) 
    \result[0]_i_102 
       (.I0(store_data[2]),
        .I1(register_a[2]),
        .I2(operand_a1),
        .I3(result[2]),
        .I4(store_data[3]),
        .I5(\read_input[3]_i_1_n_0 ),
        .O(\result[0]_i_102_n_0 ));
  LUT6 #(
    .INIT(64'h44444444DDD444D4)) 
    \result[0]_i_103 
       (.I0(store_data[1]),
        .I1(\read_input[1]_i_1_n_0 ),
        .I2(register_a[0]),
        .I3(operand_a1),
        .I4(result[0]),
        .I5(store_data[0]),
        .O(\result[0]_i_103_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_104 
       (.I0(\result[0]_i_115_n_0 ),
        .I1(register_a[6]),
        .I2(operand_a1),
        .I3(register_b[6]),
        .I4(operand_b1),
        .I5(result[6]),
        .O(\result[0]_i_104_n_0 ));
  LUT6 #(
    .INIT(64'h9099900009000999)) 
    \result[0]_i_105 
       (.I0(store_data[4]),
        .I1(\read_input[4]_i_1_n_0 ),
        .I2(result[5]),
        .I3(operand_b1),
        .I4(register_b[5]),
        .I5(\read_input[5]_i_1_n_0 ),
        .O(\result[0]_i_105_n_0 ));
  LUT6 #(
    .INIT(64'hE21D00000000E21D)) 
    \result[0]_i_106 
       (.I0(register_a[3]),
        .I1(operand_a1),
        .I2(result[3]),
        .I3(store_data[3]),
        .I4(\read_input[2]_i_1_n_0 ),
        .I5(store_data[2]),
        .O(\result[0]_i_106_n_0 ));
  LUT6 #(
    .INIT(64'hE21D00000000E21D)) 
    \result[0]_i_107 
       (.I0(register_a[1]),
        .I1(operand_a1),
        .I2(result[1]),
        .I3(store_data[1]),
        .I4(\read_input[0]_i_1_n_0 ),
        .I5(store_data[0]),
        .O(\result[0]_i_107_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[0]_i_108 
       (.I0(result[11]),
        .I1(operand_b1),
        .I2(register_b[11]),
        .I3(operand_a1),
        .I4(register_a[11]),
        .O(\result[0]_i_108_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[0]_i_109 
       (.I0(result[8]),
        .I1(operand_b1),
        .I2(register_b[8]),
        .I3(operand_a1),
        .I4(register_a[8]),
        .O(\result[0]_i_109_n_0 ));
  LUT6 #(
    .INIT(64'h4555454545555555)) 
    \result[0]_i_11 
       (.I0(opcode_2[1]),
        .I1(opcode_2[4]),
        .I2(opcode_2[0]),
        .I3(\read_input[0]_i_1_n_0 ),
        .I4(opcode_2[2]),
        .I5(\result_reg[1]_i_6_n_7 ),
        .O(\result[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_110 
       (.I0(\result[0]_i_115_n_0 ),
        .I1(register_a[6]),
        .I2(operand_a1),
        .I3(register_b[6]),
        .I4(operand_b1),
        .I5(result[6]),
        .O(\result[0]_i_110_n_0 ));
  LUT6 #(
    .INIT(64'h9099900009000999)) 
    \result[0]_i_111 
       (.I0(store_data[4]),
        .I1(\read_input[4]_i_1_n_0 ),
        .I2(result[5]),
        .I3(operand_b1),
        .I4(register_b[5]),
        .I5(\read_input[5]_i_1_n_0 ),
        .O(\result[0]_i_111_n_0 ));
  LUT6 #(
    .INIT(64'hE21D00000000E21D)) 
    \result[0]_i_112 
       (.I0(register_a[3]),
        .I1(operand_a1),
        .I2(result[3]),
        .I3(store_data[3]),
        .I4(\read_input[2]_i_1_n_0 ),
        .I5(store_data[2]),
        .O(\result[0]_i_112_n_0 ));
  LUT6 #(
    .INIT(64'hE21D00000000E21D)) 
    \result[0]_i_113 
       (.I0(register_a[1]),
        .I1(operand_a1),
        .I2(result[1]),
        .I3(store_data[1]),
        .I4(\read_input[0]_i_1_n_0 ),
        .I5(store_data[0]),
        .O(\result[0]_i_113_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_114 
       (.I0(\result[0]_i_108_n_0 ),
        .I1(register_a[10]),
        .I2(operand_a1),
        .I3(register_b[10]),
        .I4(operand_b1),
        .I5(result[10]),
        .O(\result[0]_i_114_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[0]_i_115 
       (.I0(result[7]),
        .I1(operand_b1),
        .I2(register_b[7]),
        .I3(operand_a1),
        .I4(register_a[7]),
        .O(\result[0]_i_115_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[0]_i_116 
       (.I0(result[5]),
        .I1(operand_b1),
        .I2(register_b[5]),
        .I3(operand_a1),
        .I4(register_a[5]),
        .O(\result[0]_i_116_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_117 
       (.I0(\result[0]_i_115_n_0 ),
        .I1(register_a[6]),
        .I2(operand_a1),
        .I3(register_b[6]),
        .I4(operand_b1),
        .I5(result[6]),
        .O(\result[0]_i_117_n_0 ));
  LUT6 #(
    .INIT(64'h9099900009000999)) 
    \result[0]_i_118 
       (.I0(store_data[4]),
        .I1(\read_input[4]_i_1_n_0 ),
        .I2(result[5]),
        .I3(operand_b1),
        .I4(register_b[5]),
        .I5(\read_input[5]_i_1_n_0 ),
        .O(\result[0]_i_118_n_0 ));
  LUT6 #(
    .INIT(64'hE21D00000000E21D)) 
    \result[0]_i_119 
       (.I0(register_a[3]),
        .I1(operand_a1),
        .I2(result[3]),
        .I3(store_data[3]),
        .I4(\read_input[2]_i_1_n_0 ),
        .I5(store_data[2]),
        .O(\result[0]_i_119_n_0 ));
  LUT6 #(
    .INIT(64'hE21D00000000E21D)) 
    \result[0]_i_120 
       (.I0(register_a[1]),
        .I1(operand_a1),
        .I2(result[1]),
        .I3(store_data[1]),
        .I4(\read_input[0]_i_1_n_0 ),
        .I5(store_data[0]),
        .O(\result[0]_i_120_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF02470200)) 
    \result[0]_i_15 
       (.I0(result[31]),
        .I1(operand_b1),
        .I2(register_b[31]),
        .I3(operand_a1),
        .I4(register_a[31]),
        .I5(\result[0]_i_47_n_0 ),
        .O(\result[0]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h02A202A2ABFB02A2)) 
    \result[0]_i_16 
       (.I0(\read_input[29]_i_1_n_0 ),
        .I1(register_b[29]),
        .I2(operand_b1),
        .I3(result[29]),
        .I4(\read_input[28]_i_1_n_0 ),
        .I5(store_data[28]),
        .O(\result[0]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h02A202A2ABFB02A2)) 
    \result[0]_i_17 
       (.I0(\read_input[27]_i_1_n_0 ),
        .I1(register_b[27]),
        .I2(operand_b1),
        .I3(result[27]),
        .I4(\read_input[26]_i_1_n_0 ),
        .I5(store_data[26]),
        .O(\result[0]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h22222222BBB222B2)) 
    \result[0]_i_18 
       (.I0(\read_input[25]_i_1_n_0 ),
        .I1(store_data[25]),
        .I2(register_a[24]),
        .I3(operand_a1),
        .I4(result[24]),
        .I5(store_data[24]),
        .O(\result[0]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_19 
       (.I0(\result[0]_i_48_n_0 ),
        .I1(result[30]),
        .I2(operand_b1),
        .I3(register_b[30]),
        .I4(operand_a1),
        .I5(register_a[30]),
        .O(\result[0]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h7C7F7C7C7C7F7F7F)) 
    \result[0]_i_2 
       (.I0(\result[0]_i_6_n_0 ),
        .I1(opcode_2[2]),
        .I2(opcode_2[3]),
        .I3(data10),
        .I4(opcode_2[4]),
        .I5(address_b_2[0]),
        .O(\result[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_20 
       (.I0(\result[0]_i_49_n_0 ),
        .I1(result[28]),
        .I2(operand_b1),
        .I3(register_b[28]),
        .I4(operand_a1),
        .I5(register_a[28]),
        .O(\result[0]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_21 
       (.I0(\result[0]_i_50_n_0 ),
        .I1(result[26]),
        .I2(operand_b1),
        .I3(register_b[26]),
        .I4(operand_a1),
        .I5(register_a[26]),
        .O(\result[0]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EDB8ED47)) 
    \result[0]_i_22 
       (.I0(result[24]),
        .I1(operand_b1),
        .I2(register_b[24]),
        .I3(operand_a1),
        .I4(register_a[24]),
        .I5(\result[0]_i_51_n_0 ),
        .O(\result[0]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'hAAAEBABFAAAEAAAA)) 
    \result[0]_i_24 
       (.I0(\result[0]_i_47_n_0 ),
        .I1(result[31]),
        .I2(operand_a1),
        .I3(register_a[31]),
        .I4(operand_b1),
        .I5(register_b[31]),
        .O(\result[0]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_25 
       (.I0(\result[0]_i_48_n_0 ),
        .I1(result[30]),
        .I2(operand_b1),
        .I3(register_b[30]),
        .I4(operand_a1),
        .I5(register_a[30]),
        .O(\result[0]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_26 
       (.I0(\result[0]_i_49_n_0 ),
        .I1(result[28]),
        .I2(operand_b1),
        .I3(register_b[28]),
        .I4(operand_a1),
        .I5(register_a[28]),
        .O(\result[0]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_27 
       (.I0(\result[0]_i_50_n_0 ),
        .I1(result[26]),
        .I2(operand_b1),
        .I3(register_b[26]),
        .I4(operand_a1),
        .I5(register_a[26]),
        .O(\result[0]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EDB8ED47)) 
    \result[0]_i_28 
       (.I0(result[24]),
        .I1(operand_b1),
        .I2(register_b[24]),
        .I3(operand_a1),
        .I4(register_a[24]),
        .I5(\result[0]_i_51_n_0 ),
        .O(\result[0]_i_28_n_0 ));
  LUT6 #(
    .INIT(64'h777F777F777F7700)) 
    \result[0]_i_3 
       (.I0(opcode_2[2]),
        .I1(opcode_2[1]),
        .I2(\read_input[0]_i_1_n_0 ),
        .I3(store_data[0]),
        .I4(\result[0]_i_8_n_0 ),
        .I5(\result[27]_i_8_n_0 ),
        .O(\result[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_30 
       (.I0(\result[0]_i_48_n_0 ),
        .I1(result[30]),
        .I2(operand_b1),
        .I3(register_b[30]),
        .I4(operand_a1),
        .I5(register_a[30]),
        .O(\result[0]_i_30_n_0 ));
  LUT6 #(
    .INIT(64'hA8A28A80A8A2202A)) 
    \result[0]_i_31 
       (.I0(\result[0]_i_62_n_0 ),
        .I1(result[27]),
        .I2(operand_b1),
        .I3(register_b[27]),
        .I4(operand_a1),
        .I5(register_a[27]),
        .O(\result[0]_i_31_n_0 ));
  LUT6 #(
    .INIT(64'hA8A28A80A8A2202A)) 
    \result[0]_i_32 
       (.I0(\result[0]_i_63_n_0 ),
        .I1(result[26]),
        .I2(operand_b1),
        .I3(register_b[26]),
        .I4(operand_a1),
        .I5(register_a[26]),
        .O(\result[0]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_34 
       (.I0(\result[0]_i_48_n_0 ),
        .I1(result[30]),
        .I2(operand_b1),
        .I3(register_b[30]),
        .I4(operand_a1),
        .I5(register_a[30]),
        .O(\result[0]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_35 
       (.I0(\result[0]_i_49_n_0 ),
        .I1(result[28]),
        .I2(operand_b1),
        .I3(register_b[28]),
        .I4(operand_a1),
        .I5(register_a[28]),
        .O(\result[0]_i_35_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_36 
       (.I0(\result[0]_i_50_n_0 ),
        .I1(result[26]),
        .I2(operand_b1),
        .I3(register_b[26]),
        .I4(operand_a1),
        .I5(register_a[26]),
        .O(\result[0]_i_36_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EDB8ED47)) 
    \result[0]_i_37 
       (.I0(result[24]),
        .I1(operand_b1),
        .I2(register_b[24]),
        .I3(operand_a1),
        .I4(register_a[24]),
        .I5(\result[0]_i_51_n_0 ),
        .O(\result[0]_i_37_n_0 ));
  LUT6 #(
    .INIT(64'h222222B2B2B222B2)) 
    \result[0]_i_39 
       (.I0(\read_input[23]_i_1_n_0 ),
        .I1(store_data[23]),
        .I2(\read_input[22]_i_1_n_0 ),
        .I3(register_b[22]),
        .I4(operand_b1),
        .I5(result[22]),
        .O(\result[0]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'h0A80AAAA0080AAAA)) 
    \result[0]_i_4 
       (.I0(\result[0]_i_9_n_0 ),
        .I1(data12),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(\result[0]_i_11_n_0 ),
        .I5(data4),
        .O(\result[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h222222B2B2B222B2)) 
    \result[0]_i_40 
       (.I0(\read_input[21]_i_1_n_0 ),
        .I1(store_data[21]),
        .I2(\read_input[20]_i_1_n_0 ),
        .I3(register_b[20]),
        .I4(operand_b1),
        .I5(result[20]),
        .O(\result[0]_i_40_n_0 ));
  LUT6 #(
    .INIT(64'h222222B2B2B222B2)) 
    \result[0]_i_41 
       (.I0(\read_input[19]_i_1_n_0 ),
        .I1(store_data[19]),
        .I2(\read_input[18]_i_1_n_0 ),
        .I3(register_b[18]),
        .I4(operand_b1),
        .I5(result[18]),
        .O(\result[0]_i_41_n_0 ));
  LUT6 #(
    .INIT(64'h222222B2B2B222B2)) 
    \result[0]_i_42 
       (.I0(\read_input[17]_i_1_n_0 ),
        .I1(store_data[17]),
        .I2(\read_input[16]_i_1_n_0 ),
        .I3(register_b[16]),
        .I4(operand_b1),
        .I5(result[16]),
        .O(\result[0]_i_42_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_43 
       (.I0(\result[0]_i_78_n_0 ),
        .I1(result[22]),
        .I2(operand_b1),
        .I3(register_b[22]),
        .I4(operand_a1),
        .I5(register_a[22]),
        .O(\result[0]_i_43_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EDB8ED47)) 
    \result[0]_i_44 
       (.I0(result[21]),
        .I1(operand_b1),
        .I2(register_b[21]),
        .I3(operand_a1),
        .I4(register_a[21]),
        .I5(\result[0]_i_79_n_0 ),
        .O(\result[0]_i_44_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_45 
       (.I0(\result[0]_i_80_n_0 ),
        .I1(result[18]),
        .I2(operand_b1),
        .I3(register_b[18]),
        .I4(operand_a1),
        .I5(register_a[18]),
        .O(\result[0]_i_45_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_46 
       (.I0(\result[0]_i_81_n_0 ),
        .I1(result[16]),
        .I2(operand_b1),
        .I3(register_b[16]),
        .I4(operand_a1),
        .I5(register_a[16]),
        .O(\result[0]_i_46_n_0 ));
  LUT6 #(
    .INIT(64'h0000000002470200)) 
    \result[0]_i_47 
       (.I0(result[30]),
        .I1(operand_b1),
        .I2(register_b[30]),
        .I3(operand_a1),
        .I4(register_a[30]),
        .I5(\result[0]_i_48_n_0 ),
        .O(\result[0]_i_47_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[0]_i_48 
       (.I0(register_a[31]),
        .I1(operand_a1),
        .I2(register_b[31]),
        .I3(operand_b1),
        .I4(result[31]),
        .O(\result[0]_i_48_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[0]_i_49 
       (.I0(register_a[29]),
        .I1(operand_a1),
        .I2(register_b[29]),
        .I3(operand_b1),
        .I4(result[29]),
        .O(\result[0]_i_49_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \result[0]_i_5 
       (.I0(load_data[0]),
        .I1(\state_reg_n_0_[1] ),
        .I2(OUT1[0]),
        .I3(\state_reg_n_0_[2] ),
        .O(\result[0]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[0]_i_50 
       (.I0(register_a[27]),
        .I1(operand_a1),
        .I2(register_b[27]),
        .I3(operand_b1),
        .I4(result[27]),
        .O(\result[0]_i_50_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[0]_i_51 
       (.I0(register_a[25]),
        .I1(operand_a1),
        .I2(register_b[25]),
        .I3(operand_b1),
        .I4(result[25]),
        .O(\result[0]_i_51_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_53 
       (.I0(\result[0]_i_78_n_0 ),
        .I1(result[22]),
        .I2(operand_b1),
        .I3(register_b[22]),
        .I4(operand_a1),
        .I5(register_a[22]),
        .O(\result[0]_i_53_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EDB8ED47)) 
    \result[0]_i_54 
       (.I0(result[21]),
        .I1(operand_b1),
        .I2(register_b[21]),
        .I3(operand_a1),
        .I4(register_a[21]),
        .I5(\result[0]_i_79_n_0 ),
        .O(\result[0]_i_54_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_55 
       (.I0(\result[0]_i_80_n_0 ),
        .I1(result[18]),
        .I2(operand_b1),
        .I3(register_b[18]),
        .I4(operand_a1),
        .I5(register_a[18]),
        .O(\result[0]_i_55_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_56 
       (.I0(\result[0]_i_81_n_0 ),
        .I1(result[16]),
        .I2(operand_b1),
        .I3(register_b[16]),
        .I4(operand_a1),
        .I5(register_a[16]),
        .O(\result[0]_i_56_n_0 ));
  LUT6 #(
    .INIT(64'hEEE1DD2D00000000)) 
    \result[0]_i_58 
       (.I0(register_a[21]),
        .I1(operand_a1),
        .I2(register_b[21]),
        .I3(operand_b1),
        .I4(result[21]),
        .I5(\result[0]_i_91_n_0 ),
        .O(\result[0]_i_58_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000A959)) 
    \result[0]_i_59 
       (.I0(\read_input[18]_i_1_n_0 ),
        .I1(register_b[18]),
        .I2(operand_b1),
        .I3(result[18]),
        .I4(\result[0]_i_80_n_0 ),
        .I5(\result[0]_i_79_n_0 ),
        .O(\result[0]_i_59_n_0 ));
  LUT6 #(
    .INIT(64'hE200FFFFE2000000)) 
    \result[0]_i_6 
       (.I0(register_a[0]),
        .I1(operand_a1),
        .I2(result[0]),
        .I3(store_data[0]),
        .I4(opcode_2[1]),
        .I5(data6),
        .O(\result[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hEDB8ED4700000000)) 
    \result[0]_i_60 
       (.I0(result[15]),
        .I1(operand_b1),
        .I2(register_b[15]),
        .I3(operand_a1),
        .I4(register_a[15]),
        .I5(\result[0]_i_92_n_0 ),
        .O(\result[0]_i_60_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000B847)) 
    \result[0]_i_61 
       (.I0(result[12]),
        .I1(operand_b1),
        .I2(register_b[12]),
        .I3(\read_input[12]_i_1_n_0 ),
        .I4(\result[0]_i_93_n_0 ),
        .I5(\result[0]_i_94_n_0 ),
        .O(\result[0]_i_61_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_62 
       (.I0(\result[0]_i_49_n_0 ),
        .I1(result[28]),
        .I2(operand_b1),
        .I3(register_b[28]),
        .I4(operand_a1),
        .I5(register_a[28]),
        .O(\result[0]_i_62_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EDB8ED47)) 
    \result[0]_i_63 
       (.I0(result[24]),
        .I1(operand_b1),
        .I2(register_b[24]),
        .I3(operand_a1),
        .I4(register_a[24]),
        .I5(\result[0]_i_51_n_0 ),
        .O(\result[0]_i_63_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_65 
       (.I0(\result[0]_i_78_n_0 ),
        .I1(result[22]),
        .I2(operand_b1),
        .I3(register_b[22]),
        .I4(operand_a1),
        .I5(register_a[22]),
        .O(\result[0]_i_65_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EDB8ED47)) 
    \result[0]_i_66 
       (.I0(result[21]),
        .I1(operand_b1),
        .I2(register_b[21]),
        .I3(operand_a1),
        .I4(register_a[21]),
        .I5(\result[0]_i_79_n_0 ),
        .O(\result[0]_i_66_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_67 
       (.I0(\result[0]_i_80_n_0 ),
        .I1(result[18]),
        .I2(operand_b1),
        .I3(register_b[18]),
        .I4(operand_a1),
        .I5(register_a[18]),
        .O(\result[0]_i_67_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_68 
       (.I0(\result[0]_i_81_n_0 ),
        .I1(result[16]),
        .I2(operand_b1),
        .I3(register_b[16]),
        .I4(operand_a1),
        .I5(register_a[16]),
        .O(\result[0]_i_68_n_0 ));
  LUT6 #(
    .INIT(64'h444444D4D4D444D4)) 
    \result[0]_i_70 
       (.I0(store_data[15]),
        .I1(\read_input[15]_i_1_n_0 ),
        .I2(\read_input[14]_i_1_n_0 ),
        .I3(register_b[14]),
        .I4(operand_b1),
        .I5(result[14]),
        .O(\result[0]_i_70_n_0 ));
  LUT6 #(
    .INIT(64'h444444D4D4D444D4)) 
    \result[0]_i_71 
       (.I0(store_data[13]),
        .I1(\read_input[13]_i_1_n_0 ),
        .I2(\read_input[12]_i_1_n_0 ),
        .I3(register_b[12]),
        .I4(operand_b1),
        .I5(result[12]),
        .O(\result[0]_i_71_n_0 ));
  LUT6 #(
    .INIT(64'h444444D4D4D444D4)) 
    \result[0]_i_72 
       (.I0(store_data[11]),
        .I1(\read_input[11]_i_1_n_0 ),
        .I2(\read_input[10]_i_1_n_0 ),
        .I3(register_b[10]),
        .I4(operand_b1),
        .I5(result[10]),
        .O(\result[0]_i_72_n_0 ));
  LUT6 #(
    .INIT(64'h444444D4D4D444D4)) 
    \result[0]_i_73 
       (.I0(store_data[9]),
        .I1(\read_input[9]_i_1_n_0 ),
        .I2(\read_input[8]_i_1_n_0 ),
        .I3(register_b[8]),
        .I4(operand_b1),
        .I5(result[8]),
        .O(\result[0]_i_73_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE1DD2D)) 
    \result[0]_i_74 
       (.I0(register_a[15]),
        .I1(operand_a1),
        .I2(register_b[15]),
        .I3(operand_b1),
        .I4(result[15]),
        .I5(\result[0]_i_94_n_0 ),
        .O(\result[0]_i_74_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_75 
       (.I0(\result[0]_i_93_n_0 ),
        .I1(register_a[12]),
        .I2(operand_a1),
        .I3(register_b[12]),
        .I4(operand_b1),
        .I5(result[12]),
        .O(\result[0]_i_75_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_76 
       (.I0(\result[0]_i_108_n_0 ),
        .I1(register_a[10]),
        .I2(operand_a1),
        .I3(register_b[10]),
        .I4(operand_b1),
        .I5(result[10]),
        .O(\result[0]_i_76_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE1DD2D)) 
    \result[0]_i_77 
       (.I0(register_a[9]),
        .I1(operand_a1),
        .I2(register_b[9]),
        .I3(operand_b1),
        .I4(result[9]),
        .I5(\result[0]_i_109_n_0 ),
        .O(\result[0]_i_77_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[0]_i_78 
       (.I0(register_a[23]),
        .I1(operand_a1),
        .I2(register_b[23]),
        .I3(operand_b1),
        .I4(result[23]),
        .O(\result[0]_i_78_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[0]_i_79 
       (.I0(register_a[20]),
        .I1(operand_a1),
        .I2(register_b[20]),
        .I3(operand_b1),
        .I4(result[20]),
        .O(\result[0]_i_79_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    \result[0]_i_8 
       (.I0(store_data[1]),
        .I1(store_data[2]),
        .I2(store_data[3]),
        .I3(\read_input[0]_i_1_n_0 ),
        .I4(store_data[4]),
        .O(\result[0]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[0]_i_80 
       (.I0(register_a[19]),
        .I1(operand_a1),
        .I2(register_b[19]),
        .I3(operand_b1),
        .I4(result[19]),
        .O(\result[0]_i_80_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[0]_i_81 
       (.I0(register_a[17]),
        .I1(operand_a1),
        .I2(register_b[17]),
        .I3(operand_b1),
        .I4(result[17]),
        .O(\result[0]_i_81_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE1DD2D)) 
    \result[0]_i_83 
       (.I0(register_a[15]),
        .I1(operand_a1),
        .I2(register_b[15]),
        .I3(operand_b1),
        .I4(result[15]),
        .I5(\result[0]_i_94_n_0 ),
        .O(\result[0]_i_83_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_84 
       (.I0(\result[0]_i_93_n_0 ),
        .I1(register_a[12]),
        .I2(operand_a1),
        .I3(register_b[12]),
        .I4(operand_b1),
        .I5(result[12]),
        .O(\result[0]_i_84_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_85 
       (.I0(\result[0]_i_108_n_0 ),
        .I1(register_a[10]),
        .I2(operand_a1),
        .I3(register_b[10]),
        .I4(operand_b1),
        .I5(result[10]),
        .O(\result[0]_i_85_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE1DD2D)) 
    \result[0]_i_86 
       (.I0(register_a[9]),
        .I1(operand_a1),
        .I2(register_b[9]),
        .I3(operand_b1),
        .I4(result[9]),
        .I5(\result[0]_i_109_n_0 ),
        .O(\result[0]_i_86_n_0 ));
  LUT6 #(
    .INIT(64'hEDB8ED4700000000)) 
    \result[0]_i_87 
       (.I0(result[9]),
        .I1(operand_b1),
        .I2(register_b[9]),
        .I3(operand_a1),
        .I4(register_a[9]),
        .I5(\result[0]_i_114_n_0 ),
        .O(\result[0]_i_87_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000B847)) 
    \result[0]_i_88 
       (.I0(result[6]),
        .I1(operand_b1),
        .I2(register_b[6]),
        .I3(\read_input[6]_i_1_n_0 ),
        .I4(\result[0]_i_115_n_0 ),
        .I5(\result[0]_i_109_n_0 ),
        .O(\result[0]_i_88_n_0 ));
  LUT5 #(
    .INIT(32'h00009009)) 
    \result[0]_i_89 
       (.I0(store_data[3]),
        .I1(\read_input[3]_i_1_n_0 ),
        .I2(store_data[4]),
        .I3(\read_input[4]_i_1_n_0 ),
        .I4(\result[0]_i_116_n_0 ),
        .O(\result[0]_i_89_n_0 ));
  LUT6 #(
    .INIT(64'h55FFDD5F5555DD5F)) 
    \result[0]_i_9 
       (.I0(opcode_2[1]),
        .I1(data5[0]),
        .I2(program_counter_2[0]),
        .I3(opcode_2[3]),
        .I4(opcode_2[2]),
        .I5(\result_reg[3]_i_9_n_7 ),
        .O(\result[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \result[0]_i_90 
       (.I0(store_data[0]),
        .I1(\read_input[0]_i_1_n_0 ),
        .I2(store_data[1]),
        .I3(\read_input[1]_i_1_n_0 ),
        .I4(store_data[2]),
        .I5(\read_input[2]_i_1_n_0 ),
        .O(\result[0]_i_90_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_91 
       (.I0(\result[0]_i_78_n_0 ),
        .I1(result[22]),
        .I2(operand_b1),
        .I3(register_b[22]),
        .I4(operand_a1),
        .I5(register_a[22]),
        .O(\result[0]_i_91_n_0 ));
  LUT6 #(
    .INIT(64'h5451454054511015)) 
    \result[0]_i_92 
       (.I0(\result[0]_i_81_n_0 ),
        .I1(result[16]),
        .I2(operand_b1),
        .I3(register_b[16]),
        .I4(operand_a1),
        .I5(register_a[16]),
        .O(\result[0]_i_92_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[0]_i_93 
       (.I0(result[13]),
        .I1(operand_b1),
        .I2(register_b[13]),
        .I3(operand_a1),
        .I4(register_a[13]),
        .O(\result[0]_i_93_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[0]_i_94 
       (.I0(result[14]),
        .I1(operand_b1),
        .I2(register_b[14]),
        .I3(operand_a1),
        .I4(register_a[14]),
        .O(\result[0]_i_94_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE1DD2D)) 
    \result[0]_i_96 
       (.I0(register_a[15]),
        .I1(operand_a1),
        .I2(register_b[15]),
        .I3(operand_b1),
        .I4(result[15]),
        .I5(\result[0]_i_94_n_0 ),
        .O(\result[0]_i_96_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_97 
       (.I0(\result[0]_i_93_n_0 ),
        .I1(register_a[12]),
        .I2(operand_a1),
        .I3(register_b[12]),
        .I4(operand_b1),
        .I5(result[12]),
        .O(\result[0]_i_97_n_0 ));
  LUT6 #(
    .INIT(64'h5454540151510451)) 
    \result[0]_i_98 
       (.I0(\result[0]_i_108_n_0 ),
        .I1(register_a[10]),
        .I2(operand_a1),
        .I3(register_b[10]),
        .I4(operand_b1),
        .I5(result[10]),
        .O(\result[0]_i_98_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE1DD2D)) 
    \result[0]_i_99 
       (.I0(register_a[9]),
        .I1(operand_a1),
        .I2(register_b[9]),
        .I3(operand_b1),
        .I4(result[9]),
        .I5(\result[0]_i_109_n_0 ),
        .O(\result[0]_i_99_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[10]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[10]),
        .I3(\result[10]_i_2_n_0 ),
        .I4(\result[10]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[10]_i_2 
       (.I0(\result[10]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[11]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[10]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEAEAE)) 
    \result[10]_i_3 
       (.I0(\result[10]_i_6_n_0 ),
        .I1(data7[26]),
        .I2(\result[14]_i_7_n_0 ),
        .I3(store_data[10]),
        .I4(\read_input[10]_i_1_n_0 ),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[10]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \result[10]_i_4 
       (.I0(\result[10]_i_7_n_0 ),
        .I1(store_data[1]),
        .I2(\result[12]_i_7_n_0 ),
        .O(\result[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[10]_i_5 
       (.I0(store_data[10]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[11]_i_8_n_5 ),
        .I4(opcode_2[2]),
        .I5(\read_input[10]_i_1_n_0 ),
        .O(\result[10]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[10]_i_6 
       (.I0(data2[10]),
        .I1(opcode_2[3]),
        .I2(data5[10]),
        .I3(opcode_2[2]),
        .I4(\result_reg[15]_i_16_n_5 ),
        .I5(opcode_2[1]),
        .O(\result[10]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h00000B08)) 
    \result[10]_i_7 
       (.I0(\read_input[3]_i_1_n_0 ),
        .I1(store_data[2]),
        .I2(store_data[4]),
        .I3(\read_input[7]_i_1_n_0 ),
        .I4(store_data[3]),
        .O(\result[10]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[11]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[11]),
        .I3(\result[11]_i_2_n_0 ),
        .I4(\result[11]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[11]_i_10 
       (.I0(register_a[10]),
        .I1(operand_a1),
        .I2(result[10]),
        .I3(data7[26]),
        .O(\result[11]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[11]_i_11 
       (.I0(register_a[9]),
        .I1(operand_a1),
        .I2(result[9]),
        .I3(data7[25]),
        .O(\result[11]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[11]_i_12 
       (.I0(register_a[8]),
        .I1(operand_a1),
        .I2(result[8]),
        .I3(data7[24]),
        .O(\result[11]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[11]_i_2 
       (.I0(\result[11]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[12]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[11]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEAEAE)) 
    \result[11]_i_3 
       (.I0(\result[11]_i_6_n_0 ),
        .I1(data7[27]),
        .I2(\result[14]_i_7_n_0 ),
        .I3(store_data[11]),
        .I4(\read_input[11]_i_1_n_0 ),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[11]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \result[11]_i_4 
       (.I0(\result[11]_i_7_n_0 ),
        .I1(store_data[1]),
        .I2(\result[13]_i_8_n_0 ),
        .O(\result[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[11]_i_5 
       (.I0(store_data[11]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[11]_i_8_n_4 ),
        .I4(opcode_2[2]),
        .I5(\read_input[11]_i_1_n_0 ),
        .O(\result[11]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[11]_i_6 
       (.I0(data2[11]),
        .I1(opcode_2[3]),
        .I2(data5[11]),
        .I3(opcode_2[2]),
        .I4(\result_reg[15]_i_16_n_4 ),
        .I5(opcode_2[1]),
        .O(\result[11]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000030BB3088)) 
    \result[11]_i_7 
       (.I0(\read_input[4]_i_1_n_0 ),
        .I1(store_data[2]),
        .I2(\read_input[0]_i_1_n_0 ),
        .I3(store_data[3]),
        .I4(\read_input[8]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[11]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[11]_i_9 
       (.I0(register_a[11]),
        .I1(operand_a1),
        .I2(result[11]),
        .I3(data7[27]),
        .O(\result[11]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[12]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[12]),
        .I3(\result[12]_i_2_n_0 ),
        .I4(\result[12]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[12]_i_2 
       (.I0(\result[12]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[13]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[12]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEAEAE)) 
    \result[12]_i_3 
       (.I0(\result[12]_i_6_n_0 ),
        .I1(data7[28]),
        .I2(\result[14]_i_7_n_0 ),
        .I3(store_data[12]),
        .I4(\read_input[12]_i_1_n_0 ),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[12]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \result[12]_i_4 
       (.I0(\result[12]_i_7_n_0 ),
        .I1(store_data[1]),
        .I2(\result[14]_i_8_n_0 ),
        .O(\result[12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[12]_i_5 
       (.I0(store_data[12]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[15]_i_10_n_7 ),
        .I4(opcode_2[2]),
        .I5(\read_input[12]_i_1_n_0 ),
        .O(\result[12]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[12]_i_6 
       (.I0(data2[12]),
        .I1(opcode_2[3]),
        .I2(data5[12]),
        .I3(opcode_2[2]),
        .I4(\result_reg[15]_i_8_n_7 ),
        .I5(opcode_2[1]),
        .O(\result[12]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000030BB3088)) 
    \result[12]_i_7 
       (.I0(\read_input[5]_i_1_n_0 ),
        .I1(store_data[2]),
        .I2(\read_input[1]_i_1_n_0 ),
        .I3(store_data[3]),
        .I4(\read_input[9]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[12]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF8F88888888)) 
    \result[13]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[13]),
        .I2(\result[13]_i_2_n_0 ),
        .I3(\result[13]_i_3_n_0 ),
        .I4(\result[13]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[13]_i_2 
       (.I0(\result[14]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[13]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[13]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000004)) 
    \result[13]_i_3 
       (.I0(opcode_2[0]),
        .I1(data7[29]),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(opcode_2[4]),
        .I5(\result[13]_i_7_n_0 ),
        .O(\result[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[13]_i_4 
       (.I0(data2[13]),
        .I1(opcode_2[3]),
        .I2(data5[13]),
        .I3(opcode_2[2]),
        .I4(\result_reg[15]_i_8_n_6 ),
        .I5(opcode_2[1]),
        .O(\result[13]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \result[13]_i_5 
       (.I0(\result[13]_i_8_n_0 ),
        .I1(store_data[1]),
        .I2(\result[15]_i_9_n_0 ),
        .I3(store_data[2]),
        .I4(\result[19]_i_9_n_0 ),
        .O(\result[13]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[13]_i_6 
       (.I0(store_data[13]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[15]_i_10_n_6 ),
        .I4(opcode_2[2]),
        .I5(\read_input[13]_i_1_n_0 ),
        .O(\result[13]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000A8B8A800)) 
    \result[13]_i_7 
       (.I0(result[13]),
        .I1(operand_b1),
        .I2(register_b[13]),
        .I3(operand_a1),
        .I4(register_a[13]),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[13]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000030BB3088)) 
    \result[13]_i_8 
       (.I0(\read_input[6]_i_1_n_0 ),
        .I1(store_data[2]),
        .I2(\read_input[2]_i_1_n_0 ),
        .I3(store_data[3]),
        .I4(\read_input[10]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[13]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[14]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[14]),
        .I3(\result[14]_i_2_n_0 ),
        .I4(\result[14]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[14]_i_2 
       (.I0(\result[15]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[14]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[14]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEAEAE)) 
    \result[14]_i_3 
       (.I0(\result[14]_i_6_n_0 ),
        .I1(data7[30]),
        .I2(\result[14]_i_7_n_0 ),
        .I3(store_data[14]),
        .I4(\read_input[14]_i_1_n_0 ),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[14]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \result[14]_i_4 
       (.I0(\result[14]_i_8_n_0 ),
        .I1(store_data[1]),
        .I2(\result[16]_i_8_n_0 ),
        .I3(store_data[2]),
        .I4(\result[20]_i_7_n_0 ),
        .O(\result[14]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[14]_i_5 
       (.I0(store_data[14]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[15]_i_10_n_5 ),
        .I4(opcode_2[2]),
        .I5(\read_input[14]_i_1_n_0 ),
        .O(\result[14]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[14]_i_6 
       (.I0(data2[14]),
        .I1(opcode_2[3]),
        .I2(data5[14]),
        .I3(opcode_2[2]),
        .I4(\result_reg[15]_i_8_n_5 ),
        .I5(opcode_2[1]),
        .O(\result[14]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \result[14]_i_7 
       (.I0(opcode_2[0]),
        .I1(opcode_2[4]),
        .I2(opcode_2[3]),
        .I3(opcode_2[2]),
        .O(\result[14]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000033B800B8)) 
    \result[14]_i_8 
       (.I0(\read_input[7]_i_1_n_0 ),
        .I1(store_data[2]),
        .I2(\read_input[11]_i_1_n_0 ),
        .I3(store_data[3]),
        .I4(\read_input[3]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[14]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF8F88888888)) 
    \result[15]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[15]),
        .I2(\result[15]_i_2_n_0 ),
        .I3(\result[15]_i_3_n_0 ),
        .I4(\result[15]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[15]_i_12 
       (.I0(register_a[15]),
        .I1(operand_a1),
        .I2(register_b[15]),
        .I3(operand_b1),
        .I4(result[15]),
        .O(\result[15]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[15]_i_13 
       (.I0(register_a[14]),
        .I1(operand_a1),
        .I2(register_b[14]),
        .I3(operand_b1),
        .I4(result[14]),
        .O(\result[15]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[15]_i_14 
       (.I0(register_a[13]),
        .I1(operand_a1),
        .I2(register_b[13]),
        .I3(operand_b1),
        .I4(result[13]),
        .O(\result[15]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[15]_i_15 
       (.I0(register_a[12]),
        .I1(operand_a1),
        .I2(register_b[12]),
        .I3(operand_b1),
        .I4(result[12]),
        .O(\result[15]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[15]_i_17 
       (.I0(result[15]),
        .I1(operand_b1),
        .I2(register_b[15]),
        .I3(operand_a1),
        .I4(register_a[15]),
        .O(\result[15]_i_17_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[15]_i_18 
       (.I0(result[14]),
        .I1(operand_b1),
        .I2(register_b[14]),
        .I3(operand_a1),
        .I4(register_a[14]),
        .O(\result[15]_i_18_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[15]_i_19 
       (.I0(result[13]),
        .I1(operand_b1),
        .I2(register_b[13]),
        .I3(operand_a1),
        .I4(register_a[13]),
        .O(\result[15]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[15]_i_2 
       (.I0(\result[16]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[15]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[15]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[15]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[15]_i_20 
       (.I0(result[12]),
        .I1(operand_b1),
        .I2(register_b[12]),
        .I3(operand_a1),
        .I4(register_a[12]),
        .O(\result[15]_i_20_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[15]_i_21 
       (.I0(register_a[15]),
        .I1(operand_a1),
        .I2(result[15]),
        .I3(data7[31]),
        .O(\result[15]_i_21_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[15]_i_22 
       (.I0(register_a[14]),
        .I1(operand_a1),
        .I2(result[14]),
        .I3(data7[30]),
        .O(\result[15]_i_22_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[15]_i_23 
       (.I0(register_a[13]),
        .I1(operand_a1),
        .I2(result[13]),
        .I3(data7[29]),
        .O(\result[15]_i_23_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[15]_i_24 
       (.I0(register_a[12]),
        .I1(operand_a1),
        .I2(result[12]),
        .I3(data7[28]),
        .O(\result[15]_i_24_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[15]_i_25 
       (.I0(register_a[11]),
        .I1(operand_a1),
        .I2(register_b[11]),
        .I3(operand_b1),
        .I4(result[11]),
        .O(\result[15]_i_25_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[15]_i_26 
       (.I0(register_a[10]),
        .I1(operand_a1),
        .I2(register_b[10]),
        .I3(operand_b1),
        .I4(result[10]),
        .O(\result[15]_i_26_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[15]_i_27 
       (.I0(register_a[9]),
        .I1(operand_a1),
        .I2(register_b[9]),
        .I3(operand_b1),
        .I4(result[9]),
        .O(\result[15]_i_27_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[15]_i_28 
       (.I0(register_a[8]),
        .I1(operand_a1),
        .I2(register_b[8]),
        .I3(operand_b1),
        .I4(result[8]),
        .O(\result[15]_i_28_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[15]_i_29 
       (.I0(result[11]),
        .I1(operand_b1),
        .I2(register_b[11]),
        .I3(operand_a1),
        .I4(register_a[11]),
        .O(\result[15]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hBABABAAAAAAABAAA)) 
    \result[15]_i_3 
       (.I0(\result[31]_i_13_n_0 ),
        .I1(\result[31]_i_12_n_0 ),
        .I2(\read_input[15]_i_1_n_0 ),
        .I3(register_b[15]),
        .I4(operand_b1),
        .I5(result[15]),
        .O(\result[15]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[15]_i_30 
       (.I0(result[10]),
        .I1(operand_b1),
        .I2(register_b[10]),
        .I3(operand_a1),
        .I4(register_a[10]),
        .O(\result[15]_i_30_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[15]_i_31 
       (.I0(result[9]),
        .I1(operand_b1),
        .I2(register_b[9]),
        .I3(operand_a1),
        .I4(register_a[9]),
        .O(\result[15]_i_31_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[15]_i_32 
       (.I0(result[8]),
        .I1(operand_b1),
        .I2(register_b[8]),
        .I3(operand_a1),
        .I4(register_a[8]),
        .O(\result[15]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[15]_i_4 
       (.I0(data2[15]),
        .I1(opcode_2[3]),
        .I2(data5[15]),
        .I3(opcode_2[2]),
        .I4(\result_reg[15]_i_8_n_4 ),
        .I5(opcode_2[1]),
        .O(\result[15]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[15]_i_5 
       (.I0(\result[15]_i_9_n_0 ),
        .I1(\result[19]_i_9_n_0 ),
        .I2(store_data[1]),
        .I3(\result[17]_i_7_n_0 ),
        .I4(store_data[2]),
        .I5(\result[21]_i_7_n_0 ),
        .O(\result[15]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[15]_i_6 
       (.I0(store_data[15]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[15]_i_10_n_4 ),
        .I4(opcode_2[2]),
        .I5(\read_input[15]_i_1_n_0 ),
        .O(\result[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000B8FFB800)) 
    \result[15]_i_9 
       (.I0(result[0]),
        .I1(operand_a1),
        .I2(register_a[0]),
        .I3(store_data[3]),
        .I4(\read_input[8]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[15]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF8F88888888)) 
    \result[16]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[16]),
        .I2(\result[16]_i_2_n_0 ),
        .I3(\result[16]_i_3_n_0 ),
        .I4(\result[16]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[16]_i_2 
       (.I0(\result[17]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[16]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[16]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[16]_i_3 
       (.I0(data2[16]),
        .I1(opcode_2[3]),
        .I2(data5[16]),
        .I3(opcode_2[2]),
        .I4(\result_reg[19]_i_7_n_7 ),
        .I5(opcode_2[1]),
        .O(\result[16]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBABABAAAAAAABAAA)) 
    \result[16]_i_4 
       (.I0(\result[31]_i_13_n_0 ),
        .I1(\result[31]_i_12_n_0 ),
        .I2(\read_input[16]_i_1_n_0 ),
        .I3(register_b[16]),
        .I4(operand_b1),
        .I5(result[16]),
        .O(\result[16]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[16]_i_5 
       (.I0(\result[16]_i_8_n_0 ),
        .I1(\result[20]_i_7_n_0 ),
        .I2(store_data[1]),
        .I3(\result[18]_i_7_n_0 ),
        .I4(store_data[2]),
        .I5(\result[22]_i_7_n_0 ),
        .O(\result[16]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8BBBBBBB8BB)) 
    \result[16]_i_6 
       (.I0(\result[16]_i_9_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[19]_i_11_n_7 ),
        .I4(opcode_2[2]),
        .I5(address_b_2[0]),
        .O(\result[16]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000B8FFB800)) 
    \result[16]_i_8 
       (.I0(result[1]),
        .I1(operand_a1),
        .I2(register_a[1]),
        .I3(store_data[3]),
        .I4(\read_input[9]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[16]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[16]_i_9 
       (.I0(result[16]),
        .I1(operand_b1),
        .I2(register_b[16]),
        .I3(operand_a1),
        .I4(register_a[16]),
        .I5(opcode_2[2]),
        .O(\result[16]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[17]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[17]),
        .I3(\result[17]_i_2_n_0 ),
        .I4(\result[17]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[17]_i_2 
       (.I0(\result[17]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[18]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[17]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF38080000)) 
    \result[17]_i_3 
       (.I0(data5[17]),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(\result_reg[19]_i_7_n_6 ),
        .I4(opcode_2[1]),
        .I5(\result[17]_i_6_n_0 ),
        .O(\result[17]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[17]_i_4 
       (.I0(\result[17]_i_7_n_0 ),
        .I1(\result[21]_i_7_n_0 ),
        .I2(store_data[1]),
        .I3(\result[19]_i_9_n_0 ),
        .I4(store_data[2]),
        .I5(\result[23]_i_9_n_0 ),
        .O(\result[17]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8BBBBBBB8BB)) 
    \result[17]_i_5 
       (.I0(\result[17]_i_8_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[19]_i_11_n_6 ),
        .I4(opcode_2[2]),
        .I5(address_b_2[1]),
        .O(\result[17]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[17]_i_6 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[17]_i_1_n_0 ),
        .I2(register_b[17]),
        .I3(operand_b1),
        .I4(result[17]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[17]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000E2FFE200)) 
    \result[17]_i_7 
       (.I0(register_a[2]),
        .I1(operand_a1),
        .I2(result[2]),
        .I3(store_data[3]),
        .I4(\read_input[10]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[17]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[17]_i_8 
       (.I0(result[17]),
        .I1(operand_b1),
        .I2(register_b[17]),
        .I3(operand_a1),
        .I4(register_a[17]),
        .I5(opcode_2[2]),
        .O(\result[17]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[18]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[18]),
        .I3(\result[18]_i_2_n_0 ),
        .I4(\result[18]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[18]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[18]_i_2 
       (.I0(\result[19]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[18]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[18]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF38080000)) 
    \result[18]_i_3 
       (.I0(data5[18]),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(\result_reg[19]_i_7_n_5 ),
        .I4(opcode_2[1]),
        .I5(\result[18]_i_6_n_0 ),
        .O(\result[18]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[18]_i_4 
       (.I0(\result[18]_i_7_n_0 ),
        .I1(\result[22]_i_7_n_0 ),
        .I2(store_data[1]),
        .I3(\result[20]_i_7_n_0 ),
        .I4(store_data[2]),
        .I5(\result[24]_i_7_n_0 ),
        .O(\result[18]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8BBBBBBB8BB)) 
    \result[18]_i_5 
       (.I0(\result[18]_i_8_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[19]_i_11_n_5 ),
        .I4(opcode_2[2]),
        .I5(address_b_2[2]),
        .O(\result[18]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[18]_i_6 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[18]_i_1_n_0 ),
        .I2(register_b[18]),
        .I3(operand_b1),
        .I4(result[18]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[18]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE222E2)) 
    \result[18]_i_7 
       (.I0(\read_input[11]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(register_a[3]),
        .I3(operand_a1),
        .I4(result[3]),
        .I5(store_data[4]),
        .O(\result[18]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[18]_i_8 
       (.I0(result[18]),
        .I1(operand_b1),
        .I2(register_b[18]),
        .I3(operand_a1),
        .I4(register_a[18]),
        .I5(opcode_2[2]),
        .O(\result[18]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[19]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[19]),
        .I3(\result[19]_i_2_n_0 ),
        .I4(\result[19]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[19]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[19]_i_10 
       (.I0(result[19]),
        .I1(operand_b1),
        .I2(register_b[19]),
        .I3(operand_a1),
        .I4(register_a[19]),
        .I5(opcode_2[2]),
        .O(\result[19]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[19]_i_12 
       (.I0(result[19]),
        .I1(operand_b1),
        .I2(register_b[19]),
        .I3(operand_a1),
        .I4(register_a[19]),
        .O(\result[19]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[19]_i_13 
       (.I0(result[18]),
        .I1(operand_b1),
        .I2(register_b[18]),
        .I3(operand_a1),
        .I4(register_a[18]),
        .O(\result[19]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[19]_i_14 
       (.I0(result[17]),
        .I1(operand_b1),
        .I2(register_b[17]),
        .I3(operand_a1),
        .I4(register_a[17]),
        .O(\result[19]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[19]_i_15 
       (.I0(result[16]),
        .I1(operand_b1),
        .I2(register_b[16]),
        .I3(operand_a1),
        .I4(register_a[16]),
        .O(\result[19]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[19]_i_16 
       (.I0(register_a[19]),
        .I1(operand_a1),
        .I2(register_b[19]),
        .I3(operand_b1),
        .I4(result[19]),
        .O(\result[19]_i_16_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[19]_i_17 
       (.I0(register_a[18]),
        .I1(operand_a1),
        .I2(register_b[18]),
        .I3(operand_b1),
        .I4(result[18]),
        .O(\result[19]_i_17_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[19]_i_18 
       (.I0(register_a[17]),
        .I1(operand_a1),
        .I2(register_b[17]),
        .I3(operand_b1),
        .I4(result[17]),
        .O(\result[19]_i_18_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[19]_i_19 
       (.I0(register_a[16]),
        .I1(operand_a1),
        .I2(register_b[16]),
        .I3(operand_b1),
        .I4(result[16]),
        .O(\result[19]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[19]_i_2 
       (.I0(\result[20]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[19]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[19]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[19]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[19]_i_20 
       (.I0(result[19]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[19]),
        .O(\result[19]_i_20_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[19]_i_21 
       (.I0(result[18]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[18]),
        .O(\result[19]_i_21_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[19]_i_22 
       (.I0(result[17]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[17]),
        .O(\result[19]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[19]_i_23 
       (.I0(result[16]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[16]),
        .O(\result[19]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF38080000)) 
    \result[19]_i_3 
       (.I0(data5[19]),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(\result_reg[19]_i_7_n_4 ),
        .I4(opcode_2[1]),
        .I5(\result[19]_i_8_n_0 ),
        .O(\result[19]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[19]_i_4 
       (.I0(\result[19]_i_9_n_0 ),
        .I1(\result[23]_i_9_n_0 ),
        .I2(store_data[1]),
        .I3(\result[21]_i_7_n_0 ),
        .I4(store_data[2]),
        .I5(\result[25]_i_7_n_0 ),
        .O(\result[19]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8BBBBBBB8BB)) 
    \result[19]_i_5 
       (.I0(\result[19]_i_10_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[19]_i_11_n_4 ),
        .I4(opcode_2[2]),
        .I5(address_b_2[3]),
        .O(\result[19]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[19]_i_8 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[19]_i_1_n_0 ),
        .I2(register_b[19]),
        .I3(operand_b1),
        .I4(result[19]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[19]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00000000E2FFE200)) 
    \result[19]_i_9 
       (.I0(register_a[4]),
        .I1(operand_a1),
        .I2(result[4]),
        .I3(store_data[3]),
        .I4(\read_input[12]_i_1_n_0 ),
        .I5(store_data[4]),
        .O(\result[19]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFA20000)) 
    \result[1]_i_1 
       (.I0(opcode_2[0]),
        .I1(\result[1]_i_2_n_0 ),
        .I2(\result[1]_i_3_n_0 ),
        .I3(\result[1]_i_4_n_0 ),
        .I4(\state_reg_n_0_[0] ),
        .I5(\result[1]_i_5_n_0 ),
        .O(\result[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[1]_i_10 
       (.I0(register_a[3]),
        .I1(operand_a1),
        .I2(result[3]),
        .I3(address_b_2[3]),
        .O(\result[1]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[1]_i_11 
       (.I0(register_a[2]),
        .I1(operand_a1),
        .I2(result[2]),
        .I3(address_b_2[2]),
        .O(\result[1]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[1]_i_12 
       (.I0(register_a[1]),
        .I1(operand_a1),
        .I2(result[1]),
        .I3(address_b_2[1]),
        .O(\result[1]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[1]_i_13 
       (.I0(register_a[0]),
        .I1(operand_a1),
        .I2(result[0]),
        .I3(address_b_2[0]),
        .O(\result[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[1]_i_2 
       (.I0(store_data[1]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[1]_i_6_n_6 ),
        .I4(opcode_2[2]),
        .I5(\read_input[1]_i_1_n_0 ),
        .O(\result[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000C000A)) 
    \result[1]_i_3 
       (.I0(\result[1]_i_7_n_0 ),
        .I1(\result[1]_i_8_n_0 ),
        .I2(store_data[2]),
        .I3(store_data[1]),
        .I4(store_data[0]),
        .I5(\result[27]_i_8_n_0 ),
        .O(\result[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEAEAE)) 
    \result[1]_i_4 
       (.I0(\result[1]_i_9_n_0 ),
        .I1(address_b_2[1]),
        .I2(\result[14]_i_7_n_0 ),
        .I3(store_data[1]),
        .I4(\read_input[1]_i_1_n_0 ),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[1]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \result[1]_i_5 
       (.I0(load_data[1]),
        .I1(\state_reg_n_0_[1] ),
        .I2(OUT1[1]),
        .I3(\state_reg_n_0_[2] ),
        .O(\result[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0030000000305050)) 
    \result[1]_i_7 
       (.I0(register_b[3]),
        .I1(result[3]),
        .I2(\read_input[1]_i_1_n_0 ),
        .I3(result[4]),
        .I4(operand_b1),
        .I5(register_b[4]),
        .O(\result[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0030000000305050)) 
    \result[1]_i_8 
       (.I0(register_b[3]),
        .I1(result[3]),
        .I2(\read_input[0]_i_1_n_0 ),
        .I3(result[4]),
        .I4(operand_b1),
        .I5(register_b[4]),
        .O(\result[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[1]_i_9 
       (.I0(data2[1]),
        .I1(opcode_2[3]),
        .I2(data5[1]),
        .I3(opcode_2[2]),
        .I4(\result_reg[3]_i_9_n_6 ),
        .I5(opcode_2[1]),
        .O(\result[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \result[20]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[20]),
        .I2(\result[20]_i_2_n_0 ),
        .I3(\result[20]_i_3_n_0 ),
        .I4(\result[20]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[20]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[20]_i_2 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[20]_i_1_n_0 ),
        .I2(register_b[20]),
        .I3(operand_b1),
        .I4(result[20]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[20]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[20]_i_3 
       (.I0(\result[20]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[21]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[20]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[20]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0A800080)) 
    \result[20]_i_4 
       (.I0(opcode_2[1]),
        .I1(\result_reg[23]_i_7_n_7 ),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(data5[20]),
        .O(\result[20]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[20]_i_5 
       (.I0(\result[20]_i_7_n_0 ),
        .I1(\result[24]_i_7_n_0 ),
        .I2(store_data[1]),
        .I3(\result[22]_i_7_n_0 ),
        .I4(store_data[2]),
        .I5(\result[26]_i_7_n_0 ),
        .O(\result[20]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hCFC0CFCFCFC5CFC5)) 
    \result[20]_i_6 
       (.I0(\result_reg[23]_i_10_n_7 ),
        .I1(\result[20]_i_8_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[20]),
        .I5(opcode_2[2]),
        .O(\result[20]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000BBB888B8)) 
    \result[20]_i_7 
       (.I0(\read_input[5]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(register_a[13]),
        .I3(operand_a1),
        .I4(result[13]),
        .I5(store_data[4]),
        .O(\result[20]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[20]_i_8 
       (.I0(result[20]),
        .I1(operand_b1),
        .I2(register_b[20]),
        .I3(operand_a1),
        .I4(register_a[20]),
        .I5(opcode_2[2]),
        .O(\result[20]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \result[21]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[21]),
        .I2(\result[21]_i_2_n_0 ),
        .I3(\result[21]_i_3_n_0 ),
        .I4(\result[21]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[21]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[21]_i_2 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[21]_i_1_n_0 ),
        .I2(register_b[21]),
        .I3(operand_b1),
        .I4(result[21]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[21]_i_3 
       (.I0(\result[22]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[21]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[21]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[21]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0A800080)) 
    \result[21]_i_4 
       (.I0(opcode_2[1]),
        .I1(\result_reg[23]_i_7_n_6 ),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(data5[21]),
        .O(\result[21]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[21]_i_5 
       (.I0(\result[21]_i_7_n_0 ),
        .I1(\result[25]_i_7_n_0 ),
        .I2(store_data[1]),
        .I3(\result[23]_i_9_n_0 ),
        .I4(store_data[2]),
        .I5(\result[27]_i_12_n_0 ),
        .O(\result[21]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hCFC0CFCFCFC5CFC5)) 
    \result[21]_i_6 
       (.I0(\result_reg[23]_i_10_n_6 ),
        .I1(\result[21]_i_8_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[21]),
        .I5(opcode_2[2]),
        .O(\result[21]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000BBB888B8)) 
    \result[21]_i_7 
       (.I0(\read_input[6]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(register_a[14]),
        .I3(operand_a1),
        .I4(result[14]),
        .I5(store_data[4]),
        .O(\result[21]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[21]_i_8 
       (.I0(result[21]),
        .I1(operand_b1),
        .I2(register_b[21]),
        .I3(operand_a1),
        .I4(register_a[21]),
        .I5(opcode_2[2]),
        .O(\result[21]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \result[22]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[22]),
        .I2(\result[22]_i_2_n_0 ),
        .I3(\result[22]_i_3_n_0 ),
        .I4(\result[22]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[22]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[22]_i_2 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[22]_i_1_n_0 ),
        .I2(register_b[22]),
        .I3(operand_b1),
        .I4(result[22]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[22]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[22]_i_3 
       (.I0(\result[22]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[23]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[22]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[22]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0A800080)) 
    \result[22]_i_4 
       (.I0(opcode_2[1]),
        .I1(\result_reg[23]_i_7_n_5 ),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(data5[22]),
        .O(\result[22]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[22]_i_5 
       (.I0(\result[22]_i_7_n_0 ),
        .I1(\result[26]_i_7_n_0 ),
        .I2(store_data[1]),
        .I3(\result[24]_i_7_n_0 ),
        .I4(store_data[2]),
        .I5(\result[27]_i_16_n_0 ),
        .O(\result[22]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hCFC0CFCFCFC5CFC5)) 
    \result[22]_i_6 
       (.I0(\result_reg[23]_i_10_n_5 ),
        .I1(\result[22]_i_8_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[22]),
        .I5(opcode_2[2]),
        .O(\result[22]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000BBB888B8)) 
    \result[22]_i_7 
       (.I0(\read_input[7]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(register_a[15]),
        .I3(operand_a1),
        .I4(result[15]),
        .I5(store_data[4]),
        .O(\result[22]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[22]_i_8 
       (.I0(result[22]),
        .I1(operand_b1),
        .I2(register_b[22]),
        .I3(operand_a1),
        .I4(register_a[22]),
        .I5(opcode_2[2]),
        .O(\result[22]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \result[23]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[23]),
        .I2(\result[23]_i_2_n_0 ),
        .I3(\result[23]_i_3_n_0 ),
        .I4(\result[23]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[23]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[23]_i_11 
       (.I0(result[23]),
        .I1(operand_b1),
        .I2(register_b[23]),
        .I3(operand_a1),
        .I4(register_a[23]),
        .I5(opcode_2[2]),
        .O(\result[23]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[23]_i_12 
       (.I0(register_a[23]),
        .I1(operand_a1),
        .I2(register_b[23]),
        .I3(operand_b1),
        .I4(result[23]),
        .O(\result[23]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[23]_i_13 
       (.I0(register_a[22]),
        .I1(operand_a1),
        .I2(register_b[22]),
        .I3(operand_b1),
        .I4(result[22]),
        .O(\result[23]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[23]_i_14 
       (.I0(register_a[21]),
        .I1(operand_a1),
        .I2(register_b[21]),
        .I3(operand_b1),
        .I4(result[21]),
        .O(\result[23]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[23]_i_15 
       (.I0(register_a[20]),
        .I1(operand_a1),
        .I2(register_b[20]),
        .I3(operand_b1),
        .I4(result[20]),
        .O(\result[23]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[23]_i_16 
       (.I0(result[23]),
        .I1(operand_b1),
        .I2(register_b[23]),
        .I3(operand_a1),
        .I4(register_a[23]),
        .O(\result[23]_i_16_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[23]_i_17 
       (.I0(result[22]),
        .I1(operand_b1),
        .I2(register_b[22]),
        .I3(operand_a1),
        .I4(register_a[22]),
        .O(\result[23]_i_17_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[23]_i_18 
       (.I0(result[21]),
        .I1(operand_b1),
        .I2(register_b[21]),
        .I3(operand_a1),
        .I4(register_a[21]),
        .O(\result[23]_i_18_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[23]_i_19 
       (.I0(result[20]),
        .I1(operand_b1),
        .I2(register_b[20]),
        .I3(operand_a1),
        .I4(register_a[20]),
        .O(\result[23]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[23]_i_2 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[23]_i_1_n_0 ),
        .I2(register_b[23]),
        .I3(operand_b1),
        .I4(result[23]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[23]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[23]_i_20 
       (.I0(result[23]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[23]),
        .O(\result[23]_i_20_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[23]_i_21 
       (.I0(result[22]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[22]),
        .O(\result[23]_i_21_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[23]_i_22 
       (.I0(result[21]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[21]),
        .O(\result[23]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[23]_i_23 
       (.I0(result[20]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[20]),
        .O(\result[23]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[23]_i_3 
       (.I0(\result[24]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[23]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[23]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[23]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0A800080)) 
    \result[23]_i_4 
       (.I0(opcode_2[1]),
        .I1(\result_reg[23]_i_7_n_4 ),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(data5[23]),
        .O(\result[23]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[23]_i_5 
       (.I0(\result[23]_i_9_n_0 ),
        .I1(\result[27]_i_12_n_0 ),
        .I2(store_data[1]),
        .I3(\result[25]_i_7_n_0 ),
        .I4(store_data[2]),
        .I5(\result[27]_i_14_n_0 ),
        .O(\result[23]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hCFC0CFCFCFC5CFC5)) 
    \result[23]_i_6 
       (.I0(\result_reg[23]_i_10_n_4 ),
        .I1(\result[23]_i_11_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[23]),
        .I5(opcode_2[2]),
        .O(\result[23]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \result[23]_i_9 
       (.I0(\read_input[8]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(\read_input[0]_i_1_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[16]_i_1_n_0 ),
        .O(\result[23]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \result[24]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[24]),
        .I2(\result[24]_i_2_n_0 ),
        .I3(\result[24]_i_3_n_0 ),
        .I4(\result[24]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[24]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF54040000)) 
    \result[24]_i_2 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(register_a[24]),
        .I2(operand_a1),
        .I3(result[24]),
        .I4(store_data[24]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[24]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[24]_i_3 
       (.I0(\result[24]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[25]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[24]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[24]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0A800080)) 
    \result[24]_i_4 
       (.I0(opcode_2[1]),
        .I1(\result_reg[27]_i_10_n_7 ),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(data5[24]),
        .O(\result[24]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[24]_i_5 
       (.I0(\result[24]_i_7_n_0 ),
        .I1(\result[27]_i_16_n_0 ),
        .I2(store_data[1]),
        .I3(\result[26]_i_7_n_0 ),
        .I4(store_data[2]),
        .I5(\result[27]_i_18_n_0 ),
        .O(\result[24]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hCFC0CFCFCFC5CFC5)) 
    \result[24]_i_6 
       (.I0(\result_reg[31]_i_16_n_7 ),
        .I1(\result[24]_i_8_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[24]),
        .I5(opcode_2[2]),
        .O(\result[24]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \result[24]_i_7 
       (.I0(\read_input[9]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(\read_input[1]_i_1_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[17]_i_1_n_0 ),
        .O(\result[24]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[24]_i_8 
       (.I0(result[24]),
        .I1(operand_b1),
        .I2(register_b[24]),
        .I3(operand_a1),
        .I4(register_a[24]),
        .I5(opcode_2[2]),
        .O(\result[24]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \result[25]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[25]),
        .I2(\result[25]_i_2_n_0 ),
        .I3(\result[25]_i_3_n_0 ),
        .I4(\result[25]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[25]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF54040000)) 
    \result[25]_i_2 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(register_a[25]),
        .I2(operand_a1),
        .I3(result[25]),
        .I4(store_data[25]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[25]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[25]_i_3 
       (.I0(\result[25]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[26]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[25]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[25]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0A800080)) 
    \result[25]_i_4 
       (.I0(opcode_2[1]),
        .I1(\result_reg[27]_i_10_n_6 ),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(data5[25]),
        .O(\result[25]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[25]_i_5 
       (.I0(\result[25]_i_7_n_0 ),
        .I1(\result[27]_i_14_n_0 ),
        .I2(store_data[1]),
        .I3(\result[27]_i_12_n_0 ),
        .I4(store_data[2]),
        .I5(\result[27]_i_13_n_0 ),
        .O(\result[25]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hCFC0CFCFCFC5CFC5)) 
    \result[25]_i_6 
       (.I0(\result_reg[31]_i_16_n_6 ),
        .I1(\result[25]_i_8_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[25]),
        .I5(opcode_2[2]),
        .O(\result[25]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \result[25]_i_7 
       (.I0(\read_input[10]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(\read_input[2]_i_1_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[18]_i_1_n_0 ),
        .O(\result[25]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[25]_i_8 
       (.I0(result[25]),
        .I1(operand_b1),
        .I2(register_b[25]),
        .I3(operand_a1),
        .I4(register_a[25]),
        .I5(opcode_2[2]),
        .O(\result[25]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \result[26]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[26]),
        .I2(\result[26]_i_2_n_0 ),
        .I3(\result[26]_i_3_n_0 ),
        .I4(\result[26]_i_4_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[26]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF54040000)) 
    \result[26]_i_2 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(register_a[26]),
        .I2(operand_a1),
        .I3(result[26]),
        .I4(store_data[26]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[26]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[26]_i_3 
       (.I0(\result[27]_i_6_n_0 ),
        .I1(store_data[0]),
        .I2(\result[26]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[26]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[26]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0A800080)) 
    \result[26]_i_4 
       (.I0(opcode_2[1]),
        .I1(\result_reg[27]_i_10_n_5 ),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(data5[26]),
        .O(\result[26]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[26]_i_5 
       (.I0(\result[26]_i_7_n_0 ),
        .I1(\result[27]_i_18_n_0 ),
        .I2(store_data[1]),
        .I3(\result[27]_i_16_n_0 ),
        .I4(store_data[2]),
        .I5(\result[27]_i_17_n_0 ),
        .O(\result[26]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hCFC0CFCFCFC5CFC5)) 
    \result[26]_i_6 
       (.I0(\result_reg[31]_i_16_n_5 ),
        .I1(\result[26]_i_8_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[26]),
        .I5(opcode_2[2]),
        .O(\result[26]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \result[26]_i_7 
       (.I0(\read_input[11]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(\read_input[3]_i_1_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[19]_i_1_n_0 ),
        .O(\result[26]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[26]_i_8 
       (.I0(result[26]),
        .I1(operand_b1),
        .I2(register_b[26]),
        .I3(operand_a1),
        .I4(register_a[26]),
        .I5(opcode_2[2]),
        .O(\result[26]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \result[27]_i_1 
       (.I0(\result[27]_i_2_n_0 ),
        .I1(load_data[27]),
        .I2(\result[27]_i_3_n_0 ),
        .I3(\result[27]_i_4_n_0 ),
        .I4(\result[27]_i_5_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[27]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \result[27]_i_12 
       (.I0(\read_input[12]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(\read_input[4]_i_1_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[20]_i_1_n_0 ),
        .O(\result[27]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[27]_i_13 
       (.I0(\read_input[0]_i_1_n_0 ),
        .I1(\read_input[16]_i_1_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[8]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(\read_input[24]_i_1_n_0 ),
        .O(\result[27]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \result[27]_i_14 
       (.I0(\read_input[14]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(\read_input[6]_i_1_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[22]_i_1_n_0 ),
        .O(\result[27]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[27]_i_15 
       (.I0(\read_input[2]_i_1_n_0 ),
        .I1(\read_input[18]_i_1_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[10]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(\read_input[26]_i_1_n_0 ),
        .O(\result[27]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \result[27]_i_16 
       (.I0(\read_input[13]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(\read_input[5]_i_1_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[21]_i_1_n_0 ),
        .O(\result[27]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[27]_i_17 
       (.I0(\read_input[1]_i_1_n_0 ),
        .I1(\read_input[17]_i_1_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[9]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(\read_input[25]_i_1_n_0 ),
        .O(\result[27]_i_17_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \result[27]_i_18 
       (.I0(\read_input[15]_i_1_n_0 ),
        .I1(store_data[3]),
        .I2(\read_input[7]_i_1_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[23]_i_1_n_0 ),
        .O(\result[27]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[27]_i_19 
       (.I0(\read_input[3]_i_1_n_0 ),
        .I1(\read_input[19]_i_1_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[11]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(\read_input[27]_i_1_n_0 ),
        .O(\result[27]_i_19_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \result[27]_i_2 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .O(\result[27]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \result[27]_i_20 
       (.I0(store_data[29]),
        .I1(result[28]),
        .I2(operand_b1),
        .I3(register_b[28]),
        .I4(store_data[31]),
        .I5(store_data[30]),
        .O(\result[27]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \result[27]_i_21 
       (.I0(store_data[13]),
        .I1(store_data[12]),
        .I2(store_data[8]),
        .I3(store_data[9]),
        .I4(store_data[14]),
        .I5(store_data[15]),
        .O(\result[27]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \result[27]_i_22 
       (.I0(store_data[11]),
        .I1(store_data[10]),
        .I2(store_data[7]),
        .I3(opcode_2[4]),
        .I4(store_data[5]),
        .I5(store_data[6]),
        .O(\result[27]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \result[27]_i_23 
       (.I0(store_data[27]),
        .I1(result[26]),
        .I2(operand_b1),
        .I3(register_b[26]),
        .I4(store_data[21]),
        .I5(store_data[20]),
        .O(\result[27]_i_23_n_0 ));
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \result[27]_i_24 
       (.I0(register_b[24]),
        .I1(result[24]),
        .I2(register_b[25]),
        .I3(operand_b1),
        .I4(result[25]),
        .O(\result[27]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \result[27]_i_25 
       (.I0(store_data[23]),
        .I1(store_data[22]),
        .I2(store_data[18]),
        .I3(store_data[19]),
        .I4(store_data[16]),
        .I5(store_data[17]),
        .O(\result[27]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[27]_i_26 
       (.I0(result[27]),
        .I1(operand_b1),
        .I2(register_b[27]),
        .I3(operand_a1),
        .I4(register_a[27]),
        .I5(opcode_2[2]),
        .O(\result[27]_i_26_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[27]_i_27 
       (.I0(register_a[27]),
        .I1(operand_a1),
        .I2(register_b[27]),
        .I3(operand_b1),
        .I4(result[27]),
        .O(\result[27]_i_27_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[27]_i_28 
       (.I0(register_a[26]),
        .I1(operand_a1),
        .I2(register_b[26]),
        .I3(operand_b1),
        .I4(result[26]),
        .O(\result[27]_i_28_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[27]_i_29 
       (.I0(register_a[25]),
        .I1(operand_a1),
        .I2(register_b[25]),
        .I3(operand_b1),
        .I4(result[25]),
        .O(\result[27]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[27]_i_3 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[27]_i_1_n_0 ),
        .I2(register_b[27]),
        .I3(operand_b1),
        .I4(result[27]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[27]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[27]_i_30 
       (.I0(register_a[24]),
        .I1(operand_a1),
        .I2(register_b[24]),
        .I3(operand_b1),
        .I4(result[24]),
        .O(\result[27]_i_30_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[27]_i_31 
       (.I0(result[27]),
        .I1(operand_b1),
        .I2(register_b[27]),
        .I3(operand_a1),
        .I4(register_a[27]),
        .O(\result[27]_i_31_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[27]_i_32 
       (.I0(result[26]),
        .I1(operand_b1),
        .I2(register_b[26]),
        .I3(operand_a1),
        .I4(register_a[26]),
        .O(\result[27]_i_32_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[27]_i_33 
       (.I0(result[25]),
        .I1(operand_b1),
        .I2(register_b[25]),
        .I3(operand_a1),
        .I4(register_a[25]),
        .O(\result[27]_i_33_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[27]_i_34 
       (.I0(result[24]),
        .I1(operand_b1),
        .I2(register_b[24]),
        .I3(operand_a1),
        .I4(register_a[24]),
        .O(\result[27]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[27]_i_4 
       (.I0(\result[27]_i_6_n_0 ),
        .I1(store_data[0]),
        .I2(\result[27]_i_7_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[27]_i_9_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[27]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h0A800080)) 
    \result[27]_i_5 
       (.I0(opcode_2[1]),
        .I1(\result_reg[27]_i_10_n_4 ),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(data5[27]),
        .O(\result[27]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[27]_i_6 
       (.I0(\result[27]_i_12_n_0 ),
        .I1(\result[27]_i_13_n_0 ),
        .I2(store_data[1]),
        .I3(\result[27]_i_14_n_0 ),
        .I4(store_data[2]),
        .I5(\result[27]_i_15_n_0 ),
        .O(\result[27]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[27]_i_7 
       (.I0(\result[27]_i_16_n_0 ),
        .I1(\result[27]_i_17_n_0 ),
        .I2(store_data[1]),
        .I3(\result[27]_i_18_n_0 ),
        .I4(store_data[2]),
        .I5(\result[27]_i_19_n_0 ),
        .O(\result[27]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \result[27]_i_8 
       (.I0(\result[27]_i_20_n_0 ),
        .I1(\result[27]_i_21_n_0 ),
        .I2(\result[27]_i_22_n_0 ),
        .I3(\result[27]_i_23_n_0 ),
        .I4(\result[27]_i_24_n_0 ),
        .I5(\result[27]_i_25_n_0 ),
        .O(\result[27]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hCFC0CFCFCFC5CFC5)) 
    \result[27]_i_9 
       (.I0(\result_reg[31]_i_16_n_4 ),
        .I1(\result[27]_i_26_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[27]),
        .I5(opcode_2[2]),
        .O(\result[27]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFBBAAAAFFFBAAAA)) 
    \result[28]_i_1 
       (.I0(\result[28]_i_2_n_0 ),
        .I1(\result_reg[28]_i_3_n_0 ),
        .I2(opcode_2[1]),
        .I3(\result[28]_i_4_n_0 ),
        .I4(\state_reg_n_0_[0] ),
        .I5(\result[28]_i_5_n_0 ),
        .O(\result[28]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1F10FFF01F1FFFF0)) 
    \result[28]_i_10 
       (.I0(store_data[28]),
        .I1(\read_input[28]_i_1_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(opcode_2[2]),
        .I5(data7[28]),
        .O(\result[28]_i_10_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \result[28]_i_2 
       (.I0(load_data[28]),
        .I1(\state_reg_n_0_[1] ),
        .I2(\state_reg_n_0_[2] ),
        .O(\result[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF54040000)) 
    \result[28]_i_4 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(register_a[28]),
        .I2(operand_a1),
        .I3(result[28]),
        .I4(store_data[28]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[28]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hC7F7)) 
    \result[28]_i_5 
       (.I0(data5[28]),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(\result_reg[31]_i_15_n_7 ),
        .O(\result[28]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[28]_i_6 
       (.I0(\result[29]_i_8_n_0 ),
        .I1(store_data[0]),
        .I2(\result[27]_i_7_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[28]_i_9_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[28]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[28]_i_7 
       (.I0(\result[29]_i_8_n_0 ),
        .I1(store_data[0]),
        .I2(\result[27]_i_7_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[28]_i_10_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[28]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h2002000000002002)) 
    \result[28]_i_8 
       (.I0(write_enable_reg_n_0),
        .I1(\read_input[31]_i_4_n_0 ),
        .I2(address_a_2[0]),
        .I3(address_z_3[0]),
        .I4(address_a_2[3]),
        .I5(address_z_3[3]),
        .O(operand_a1));
  LUT6 #(
    .INIT(64'h1F101F1FFFFFFFFF)) 
    \result[28]_i_9 
       (.I0(store_data[28]),
        .I1(\read_input[28]_i_1_n_0 ),
        .I2(opcode_2[1]),
        .I3(opcode_2[4]),
        .I4(data7[28]),
        .I5(opcode_2[2]),
        .O(\result[28]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFBBAAAAFFFBAAAA)) 
    \result[29]_i_1 
       (.I0(\result[29]_i_2_n_0 ),
        .I1(\result_reg[29]_i_3_n_0 ),
        .I2(opcode_2[1]),
        .I3(\result[29]_i_4_n_0 ),
        .I4(\state_reg_n_0_[0] ),
        .I5(\result[29]_i_5_n_0 ),
        .O(\result[29]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8BBB8)) 
    \result[29]_i_10 
       (.I0(\result[29]_i_11_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(opcode_2[2]),
        .I4(data7[29]),
        .O(\result[29]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[29]_i_11 
       (.I0(result[29]),
        .I1(operand_b1),
        .I2(register_b[29]),
        .I3(operand_a1),
        .I4(register_a[29]),
        .I5(opcode_2[2]),
        .O(\result[29]_i_11_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \result[29]_i_2 
       (.I0(load_data[29]),
        .I1(\state_reg_n_0_[1] ),
        .I2(\state_reg_n_0_[2] ),
        .O(\result[29]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[29]_i_4 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[29]_i_1_n_0 ),
        .I2(register_b[29]),
        .I3(operand_b1),
        .I4(result[29]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[29]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hC7F7)) 
    \result[29]_i_5 
       (.I0(data5[29]),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(\result_reg[31]_i_15_n_6 ),
        .O(\result[29]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[29]_i_6 
       (.I0(\result[29]_i_8_n_0 ),
        .I1(store_data[0]),
        .I2(\result[30]_i_8_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[29]_i_9_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[29]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[29]_i_7 
       (.I0(\result[29]_i_8_n_0 ),
        .I1(store_data[0]),
        .I2(\result[30]_i_8_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[29]_i_10_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[29]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[29]_i_8 
       (.I0(\result[27]_i_14_n_0 ),
        .I1(\result[27]_i_15_n_0 ),
        .I2(store_data[1]),
        .I3(\result[27]_i_13_n_0 ),
        .I4(store_data[2]),
        .I5(\result[31]_i_39_n_0 ),
        .O(\result[29]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBBBBB)) 
    \result[29]_i_9 
       (.I0(\result[29]_i_11_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(data7[29]),
        .I4(opcode_2[2]),
        .O(\result[29]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF200)) 
    \result[2]_i_1 
       (.I0(opcode_2[0]),
        .I1(\result[2]_i_2_n_0 ),
        .I2(\result[2]_i_3_n_0 ),
        .I3(\state_reg_n_0_[0] ),
        .I4(\result[2]_i_4_n_0 ),
        .O(\result[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAA8A8888AA8AAAAA)) 
    \result[2]_i_2 
       (.I0(\result[2]_i_5_n_0 ),
        .I1(\result[27]_i_8_n_0 ),
        .I2(\result[2]_i_6_n_0 ),
        .I3(store_data[1]),
        .I4(store_data[0]),
        .I5(\result[3]_i_5_n_0 ),
        .O(\result[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF2222F222)) 
    \result[2]_i_3 
       (.I0(address_b_2[2]),
        .I1(\result[14]_i_7_n_0 ),
        .I2(store_data[2]),
        .I3(\read_input[2]_i_1_n_0 ),
        .I4(\result[31]_i_12_n_0 ),
        .I5(\result[2]_i_7_n_0 ),
        .O(\result[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \result[2]_i_4 
       (.I0(load_data[2]),
        .I1(\state_reg_n_0_[1] ),
        .I2(OUT1[2]),
        .I3(\state_reg_n_0_[2] ),
        .O(\result[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[2]_i_5 
       (.I0(store_data[2]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[1]_i_6_n_5 ),
        .I4(opcode_2[2]),
        .I5(\read_input[2]_i_1_n_0 ),
        .O(\result[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000005404)) 
    \result[2]_i_6 
       (.I0(store_data[4]),
        .I1(register_a[1]),
        .I2(operand_a1),
        .I3(result[1]),
        .I4(store_data[3]),
        .I5(store_data[2]),
        .O(\result[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[2]_i_7 
       (.I0(data2[2]),
        .I1(opcode_2[3]),
        .I2(data5[2]),
        .I3(opcode_2[2]),
        .I4(\result_reg[3]_i_9_n_5 ),
        .I5(opcode_2[1]),
        .O(\result[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFBBAAAAFFFBAAAA)) 
    \result[30]_i_1 
       (.I0(\result[30]_i_2_n_0 ),
        .I1(\result_reg[30]_i_3_n_0 ),
        .I2(opcode_2[1]),
        .I3(\result[30]_i_4_n_0 ),
        .I4(\state_reg_n_0_[0] ),
        .I5(\result[30]_i_5_n_0 ),
        .O(\result[30]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8BBB8)) 
    \result[30]_i_10 
       (.I0(\result[30]_i_11_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(opcode_2[2]),
        .I4(data7[30]),
        .O(\result[30]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[30]_i_11 
       (.I0(result[30]),
        .I1(operand_b1),
        .I2(register_b[30]),
        .I3(operand_a1),
        .I4(register_a[30]),
        .I5(opcode_2[2]),
        .O(\result[30]_i_11_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \result[30]_i_2 
       (.I0(load_data[30]),
        .I1(\state_reg_n_0_[1] ),
        .I2(\state_reg_n_0_[2] ),
        .O(\result[30]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[30]_i_4 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[30]_i_1_n_0 ),
        .I2(register_b[30]),
        .I3(operand_b1),
        .I4(result[30]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[30]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hC7F7)) 
    \result[30]_i_5 
       (.I0(data5[30]),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(\result_reg[31]_i_15_n_5 ),
        .O(\result[30]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[30]_i_6 
       (.I0(\result[31]_i_22_n_0 ),
        .I1(store_data[0]),
        .I2(\result[30]_i_8_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[30]_i_9_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[30]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[30]_i_7 
       (.I0(\result[31]_i_22_n_0 ),
        .I1(store_data[0]),
        .I2(\result[30]_i_8_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[30]_i_10_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[30]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[30]_i_8 
       (.I0(\result[27]_i_18_n_0 ),
        .I1(\result[27]_i_19_n_0 ),
        .I2(store_data[1]),
        .I3(\result[27]_i_17_n_0 ),
        .I4(store_data[2]),
        .I5(\result[31]_i_37_n_0 ),
        .O(\result[30]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBBBBB)) 
    \result[30]_i_9 
       (.I0(\result[30]_i_11_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(data7[30]),
        .I4(opcode_2[2]),
        .O(\result[30]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \result[31]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(\result[31]_i_3_n_0 ),
        .I3(\state_reg_n_0_[0] ),
        .I4(\result[31]_i_4_n_0 ),
        .O(\result[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCEFE0000FFFFFFFF)) 
    \result[31]_i_10 
       (.I0(\result[31]_i_21_n_0 ),
        .I1(\result[27]_i_8_n_0 ),
        .I2(store_data[0]),
        .I3(\result[31]_i_22_n_0 ),
        .I4(\result[31]_i_23_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[31]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hCEFE0000FFFFFFFF)) 
    \result[31]_i_11 
       (.I0(\result[31]_i_21_n_0 ),
        .I1(\result[27]_i_8_n_0 ),
        .I2(store_data[0]),
        .I3(\result[31]_i_22_n_0 ),
        .I4(\result[31]_i_24_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[31]_i_11_n_0 ));
  LUT3 #(
    .INIT(8'hBF)) 
    \result[31]_i_12 
       (.I0(opcode_2[0]),
        .I1(opcode_2[1]),
        .I2(opcode_2[3]),
        .O(\result[31]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \result[31]_i_13 
       (.I0(data7[31]),
        .I1(opcode_2[2]),
        .I2(opcode_2[3]),
        .I3(opcode_2[4]),
        .I4(opcode_2[0]),
        .O(\result[31]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[31]_i_17 
       (.I0(result[31]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[31]),
        .O(\result[31]_i_17_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[31]_i_18 
       (.I0(result[30]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[30]),
        .O(\result[31]_i_18_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[31]_i_19 
       (.I0(result[29]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[29]),
        .O(\result[31]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFFBBAAAAFFFBAAAA)) 
    \result[31]_i_2 
       (.I0(\result[31]_i_5_n_0 ),
        .I1(\result_reg[31]_i_6_n_0 ),
        .I2(opcode_2[1]),
        .I3(\result[31]_i_7_n_0 ),
        .I4(\state_reg_n_0_[0] ),
        .I5(\result[31]_i_8_n_0 ),
        .O(\result[31]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[31]_i_20 
       (.I0(result[28]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[28]),
        .O(\result[31]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \result[31]_i_21 
       (.I0(\result[27]_i_17_n_0 ),
        .I1(\result[31]_i_37_n_0 ),
        .I2(store_data[1]),
        .I3(\result[27]_i_19_n_0 ),
        .I4(store_data[2]),
        .I5(\result[31]_i_38_n_0 ),
        .O(\result[31]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[31]_i_22 
       (.I0(\result[27]_i_13_n_0 ),
        .I1(\result[31]_i_39_n_0 ),
        .I2(store_data[1]),
        .I3(\result[27]_i_15_n_0 ),
        .I4(store_data[2]),
        .I5(\result[31]_i_40_n_0 ),
        .O(\result[31]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBBBBB)) 
    \result[31]_i_23 
       (.I0(\result[31]_i_41_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(data7[31]),
        .I4(opcode_2[2]),
        .O(\result[31]_i_23_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8BBB8)) 
    \result[31]_i_24 
       (.I0(\result[31]_i_41_n_0 ),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(opcode_2[2]),
        .I4(data7[31]),
        .O(\result[31]_i_24_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[31]_i_25 
       (.I0(result[31]),
        .I1(operand_b1),
        .I2(register_b[31]),
        .I3(operand_a1),
        .I4(register_a[31]),
        .O(\result[31]_i_25_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[31]_i_26 
       (.I0(result[30]),
        .I1(operand_b1),
        .I2(register_b[30]),
        .I3(operand_a1),
        .I4(register_a[30]),
        .O(\result[31]_i_26_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[31]_i_27 
       (.I0(result[29]),
        .I1(operand_b1),
        .I2(register_b[29]),
        .I3(operand_a1),
        .I4(register_a[29]),
        .O(\result[31]_i_27_n_0 ));
  LUT5 #(
    .INIT(32'hEDB8ED47)) 
    \result[31]_i_28 
       (.I0(result[28]),
        .I1(operand_b1),
        .I2(register_b[28]),
        .I3(operand_a1),
        .I4(register_a[28]),
        .O(\result[31]_i_28_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[31]_i_29 
       (.I0(register_a[31]),
        .I1(operand_a1),
        .I2(register_b[31]),
        .I3(operand_b1),
        .I4(result[31]),
        .O(\result[31]_i_29_n_0 ));
  LUT5 #(
    .INIT(32'hBABCAF98)) 
    \result[31]_i_3 
       (.I0(opcode_2[4]),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(opcode_2[1]),
        .I4(opcode_2[0]),
        .O(\result[31]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[31]_i_30 
       (.I0(register_a[30]),
        .I1(operand_a1),
        .I2(register_b[30]),
        .I3(operand_b1),
        .I4(result[30]),
        .O(\result[31]_i_30_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[31]_i_31 
       (.I0(register_a[29]),
        .I1(operand_a1),
        .I2(register_b[29]),
        .I3(operand_b1),
        .I4(result[29]),
        .O(\result[31]_i_31_n_0 ));
  LUT5 #(
    .INIT(32'h111E22D2)) 
    \result[31]_i_32 
       (.I0(register_a[28]),
        .I1(operand_a1),
        .I2(register_b[28]),
        .I3(operand_b1),
        .I4(result[28]),
        .O(\result[31]_i_32_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[31]_i_33 
       (.I0(result[27]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[27]),
        .O(\result[31]_i_33_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[31]_i_34 
       (.I0(result[26]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[26]),
        .O(\result[31]_i_34_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[31]_i_35 
       (.I0(result[25]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[25]),
        .O(\result[31]_i_35_n_0 ));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \result[31]_i_36 
       (.I0(result[24]),
        .I1(write_enable_reg_n_0),
        .I2(\read_input[31]_i_4_n_0 ),
        .I3(\read_input[31]_i_5_n_0 ),
        .I4(register_a[24]),
        .O(\result[31]_i_36_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[31]_i_37 
       (.I0(\read_input[5]_i_1_n_0 ),
        .I1(\read_input[21]_i_1_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[13]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(\read_input[29]_i_1_n_0 ),
        .O(\result[31]_i_37_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[31]_i_38 
       (.I0(\read_input[7]_i_1_n_0 ),
        .I1(\read_input[23]_i_1_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[15]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(\read_input[31]_i_2_n_0 ),
        .O(\result[31]_i_38_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[31]_i_39 
       (.I0(\read_input[4]_i_1_n_0 ),
        .I1(\read_input[20]_i_1_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[12]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(\read_input[28]_i_1_n_0 ),
        .O(\result[31]_i_39_n_0 ));
  LUT5 #(
    .INIT(32'hD5005500)) 
    \result[31]_i_4 
       (.I0(\state_reg_n_0_[1] ),
        .I1(OUT1_STB),
        .I2(OUT1_ACK),
        .I3(\state_reg_n_0_[2] ),
        .I4(\s_input_rs232_in_ack[0]_i_2_n_0 ),
        .O(\result[31]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \result[31]_i_40 
       (.I0(\read_input[6]_i_1_n_0 ),
        .I1(\read_input[22]_i_1_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[14]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(\read_input[30]_i_1_n_0 ),
        .O(\result[31]_i_40_n_0 ));
  LUT6 #(
    .INIT(64'h45004547FFFFFFFF)) 
    \result[31]_i_41 
       (.I0(result[31]),
        .I1(operand_b1),
        .I2(register_b[31]),
        .I3(operand_a1),
        .I4(register_a[31]),
        .I5(opcode_2[2]),
        .O(\result[31]_i_41_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \result[31]_i_5 
       (.I0(load_data[31]),
        .I1(\state_reg_n_0_[1] ),
        .I2(\state_reg_n_0_[2] ),
        .O(\result[31]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44400040)) 
    \result[31]_i_7 
       (.I0(\result[31]_i_12_n_0 ),
        .I1(\read_input[31]_i_2_n_0 ),
        .I2(register_b[31]),
        .I3(operand_b1),
        .I4(result[31]),
        .I5(\result[31]_i_13_n_0 ),
        .O(\result[31]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hC7F7)) 
    \result[31]_i_8 
       (.I0(data5[31]),
        .I1(opcode_2[3]),
        .I2(opcode_2[2]),
        .I3(\result_reg[31]_i_15_n_4 ),
        .O(\result[31]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'hFFD0)) 
    \result[3]_i_1 
       (.I0(\result[3]_i_2_n_0 ),
        .I1(\result[3]_i_3_n_0 ),
        .I2(\state_reg_n_0_[0] ),
        .I3(\result[3]_i_4_n_0 ),
        .O(\result[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[3]_i_10 
       (.I0(register_a[3]),
        .I1(operand_a1),
        .I2(register_b[3]),
        .I3(operand_b1),
        .I4(result[3]),
        .O(\result[3]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[3]_i_11 
       (.I0(register_a[2]),
        .I1(operand_a1),
        .I2(register_b[2]),
        .I3(operand_b1),
        .I4(result[2]),
        .O(\result[3]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'hE21D)) 
    \result[3]_i_12 
       (.I0(register_a[1]),
        .I1(operand_a1),
        .I2(result[1]),
        .I3(store_data[1]),
        .O(\result[3]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'hE21D)) 
    \result[3]_i_13 
       (.I0(register_a[0]),
        .I1(operand_a1),
        .I2(result[0]),
        .I3(store_data[0]),
        .O(\result[3]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[3]_i_14 
       (.I0(result[3]),
        .I1(operand_b1),
        .I2(register_b[3]),
        .I3(operand_a1),
        .I4(register_a[3]),
        .O(\result[3]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[3]_i_15 
       (.I0(result[2]),
        .I1(operand_b1),
        .I2(register_b[2]),
        .I3(operand_a1),
        .I4(register_a[2]),
        .O(\result[3]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h656A)) 
    \result[3]_i_16 
       (.I0(store_data[1]),
        .I1(result[1]),
        .I2(operand_a1),
        .I3(register_a[1]),
        .O(\result[3]_i_16_n_0 ));
  LUT4 #(
    .INIT(16'h656A)) 
    \result[3]_i_17 
       (.I0(store_data[0]),
        .I1(result[0]),
        .I2(operand_a1),
        .I3(register_a[0]),
        .O(\result[3]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[3]_i_2 
       (.I0(\result[3]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[4]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[3]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF2222F222)) 
    \result[3]_i_3 
       (.I0(address_b_2[3]),
        .I1(\result[14]_i_7_n_0 ),
        .I2(store_data[3]),
        .I3(\read_input[3]_i_1_n_0 ),
        .I4(\result[31]_i_12_n_0 ),
        .I5(\result[3]_i_7_n_0 ),
        .O(\result[3]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \result[3]_i_4 
       (.I0(load_data[3]),
        .I1(\state_reg_n_0_[1] ),
        .I2(OUT1[3]),
        .I3(\state_reg_n_0_[2] ),
        .O(\result[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000B08)) 
    \result[3]_i_5 
       (.I0(\read_input[0]_i_1_n_0 ),
        .I1(store_data[1]),
        .I2(store_data[3]),
        .I3(\read_input[2]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(store_data[2]),
        .O(\result[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[3]_i_6 
       (.I0(store_data[3]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[1]_i_6_n_4 ),
        .I4(opcode_2[2]),
        .I5(\read_input[3]_i_1_n_0 ),
        .O(\result[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[3]_i_7 
       (.I0(data2[3]),
        .I1(opcode_2[3]),
        .I2(data5[3]),
        .I3(opcode_2[2]),
        .I4(\result_reg[3]_i_9_n_4 ),
        .I5(opcode_2[1]),
        .O(\result[3]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hFFD0)) 
    \result[4]_i_1 
       (.I0(\result[4]_i_2_n_0 ),
        .I1(\result[4]_i_3_n_0 ),
        .I2(\state_reg_n_0_[0] ),
        .I3(\result[4]_i_4_n_0 ),
        .O(\result[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[4]_i_2 
       (.I0(\result[5]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[4]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[4]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEAEAE)) 
    \result[4]_i_3 
       (.I0(\result[4]_i_7_n_0 ),
        .I1(data7[20]),
        .I2(\result[14]_i_7_n_0 ),
        .I3(store_data[4]),
        .I4(\read_input[4]_i_1_n_0 ),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \result[4]_i_4 
       (.I0(load_data[4]),
        .I1(\state_reg_n_0_[1] ),
        .I2(OUT1[4]),
        .I3(\state_reg_n_0_[2] ),
        .O(\result[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000B08)) 
    \result[4]_i_5 
       (.I0(\read_input[1]_i_1_n_0 ),
        .I1(store_data[1]),
        .I2(store_data[3]),
        .I3(\read_input[3]_i_1_n_0 ),
        .I4(store_data[4]),
        .I5(store_data[2]),
        .O(\result[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[4]_i_6 
       (.I0(store_data[4]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[7]_i_9_n_7 ),
        .I4(opcode_2[2]),
        .I5(\read_input[4]_i_1_n_0 ),
        .O(\result[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[4]_i_7 
       (.I0(data2[4]),
        .I1(opcode_2[3]),
        .I2(data5[4]),
        .I3(opcode_2[2]),
        .I4(\result_reg[7]_i_11_n_7 ),
        .I5(opcode_2[1]),
        .O(\result[4]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hFFD0)) 
    \result[5]_i_1 
       (.I0(\result[5]_i_2_n_0 ),
        .I1(\result[5]_i_3_n_0 ),
        .I2(\state_reg_n_0_[0] ),
        .I3(\result[5]_i_4_n_0 ),
        .O(\result[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[5]_i_2 
       (.I0(\result[6]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[5]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[5]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAEAAAEAFFFFAAEA)) 
    \result[5]_i_3 
       (.I0(\result[5]_i_7_n_0 ),
        .I1(store_data[5]),
        .I2(\read_input[5]_i_1_n_0 ),
        .I3(\result[31]_i_12_n_0 ),
        .I4(data7[21]),
        .I5(\result[14]_i_7_n_0 ),
        .O(\result[5]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \result[5]_i_4 
       (.I0(load_data[5]),
        .I1(\state_reg_n_0_[1] ),
        .I2(OUT1[5]),
        .I3(\state_reg_n_0_[2] ),
        .O(\result[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0004FFFF00040000)) 
    \result[5]_i_5 
       (.I0(store_data[3]),
        .I1(\read_input[2]_i_1_n_0 ),
        .I2(store_data[4]),
        .I3(store_data[2]),
        .I4(store_data[1]),
        .I5(\result[7]_i_8_n_0 ),
        .O(\result[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[5]_i_6 
       (.I0(store_data[5]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[7]_i_9_n_6 ),
        .I4(opcode_2[2]),
        .I5(\read_input[5]_i_1_n_0 ),
        .O(\result[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[5]_i_7 
       (.I0(data2[5]),
        .I1(opcode_2[3]),
        .I2(data5[5]),
        .I3(opcode_2[2]),
        .I4(\result_reg[7]_i_11_n_6 ),
        .I5(opcode_2[1]),
        .O(\result[5]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hFFD0)) 
    \result[6]_i_1 
       (.I0(\result[6]_i_2_n_0 ),
        .I1(\result[6]_i_3_n_0 ),
        .I2(\state_reg_n_0_[0] ),
        .I3(\result[6]_i_4_n_0 ),
        .O(\result[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[6]_i_2 
       (.I0(\result[7]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[6]_i_5_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[6]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEAEAE)) 
    \result[6]_i_3 
       (.I0(\result[6]_i_7_n_0 ),
        .I1(data7[22]),
        .I2(\result[14]_i_7_n_0 ),
        .I3(store_data[6]),
        .I4(\read_input[6]_i_1_n_0 ),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[6]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \result[6]_i_4 
       (.I0(load_data[6]),
        .I1(\state_reg_n_0_[1] ),
        .I2(OUT1[6]),
        .I3(\state_reg_n_0_[2] ),
        .O(\result[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0004FFFF00040000)) 
    \result[6]_i_5 
       (.I0(store_data[3]),
        .I1(\read_input[3]_i_1_n_0 ),
        .I2(store_data[4]),
        .I3(store_data[2]),
        .I4(store_data[1]),
        .I5(\result[8]_i_7_n_0 ),
        .O(\result[6]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[6]_i_6 
       (.I0(store_data[6]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[7]_i_9_n_5 ),
        .I4(opcode_2[2]),
        .I5(\read_input[6]_i_1_n_0 ),
        .O(\result[6]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[6]_i_7 
       (.I0(data2[6]),
        .I1(opcode_2[3]),
        .I2(data5[6]),
        .I3(opcode_2[2]),
        .I4(\result_reg[7]_i_11_n_5 ),
        .I5(opcode_2[1]),
        .O(\result[6]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hFFD0)) 
    \result[7]_i_1 
       (.I0(\result[7]_i_2_n_0 ),
        .I1(\result[7]_i_3_n_0 ),
        .I2(\state_reg_n_0_[0] ),
        .I3(\result[7]_i_4_n_0 ),
        .O(\result[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[7]_i_12 
       (.I0(register_a[7]),
        .I1(operand_a1),
        .I2(result[7]),
        .I3(data7[23]),
        .O(\result[7]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[7]_i_13 
       (.I0(register_a[6]),
        .I1(operand_a1),
        .I2(result[6]),
        .I3(data7[22]),
        .O(\result[7]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[7]_i_14 
       (.I0(register_a[5]),
        .I1(operand_a1),
        .I2(result[5]),
        .I3(data7[21]),
        .O(\result[7]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \result[7]_i_15 
       (.I0(register_a[4]),
        .I1(operand_a1),
        .I2(result[4]),
        .I3(data7[20]),
        .O(\result[7]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[7]_i_16 
       (.I0(register_a[7]),
        .I1(operand_a1),
        .I2(register_b[7]),
        .I3(operand_b1),
        .I4(result[7]),
        .O(\result[7]_i_16_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[7]_i_17 
       (.I0(register_a[6]),
        .I1(operand_a1),
        .I2(register_b[6]),
        .I3(operand_b1),
        .I4(result[6]),
        .O(\result[7]_i_17_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[7]_i_18 
       (.I0(register_a[5]),
        .I1(operand_a1),
        .I2(register_b[5]),
        .I3(operand_b1),
        .I4(result[5]),
        .O(\result[7]_i_18_n_0 ));
  LUT5 #(
    .INIT(32'hEEE1DD2D)) 
    \result[7]_i_19 
       (.I0(register_a[4]),
        .I1(operand_a1),
        .I2(register_b[4]),
        .I3(operand_b1),
        .I4(result[4]),
        .O(\result[7]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[7]_i_2 
       (.I0(\result[7]_i_5_n_0 ),
        .I1(store_data[0]),
        .I2(\result[8]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[7]_i_6_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[7]_i_20 
       (.I0(result[7]),
        .I1(operand_b1),
        .I2(register_b[7]),
        .I3(operand_a1),
        .I4(register_a[7]),
        .O(\result[7]_i_20_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[7]_i_21 
       (.I0(result[6]),
        .I1(operand_b1),
        .I2(register_b[6]),
        .I3(operand_a1),
        .I4(register_a[6]),
        .O(\result[7]_i_21_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[7]_i_22 
       (.I0(result[5]),
        .I1(operand_b1),
        .I2(register_b[5]),
        .I3(operand_a1),
        .I4(register_a[5]),
        .O(\result[7]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'h124712B8)) 
    \result[7]_i_23 
       (.I0(result[4]),
        .I1(operand_b1),
        .I2(register_b[4]),
        .I3(operand_a1),
        .I4(register_a[4]),
        .O(\result[7]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEAEAE)) 
    \result[7]_i_3 
       (.I0(\result[7]_i_7_n_0 ),
        .I1(data7[23]),
        .I2(\result[14]_i_7_n_0 ),
        .I3(store_data[7]),
        .I4(\read_input[7]_i_1_n_0 ),
        .I5(\result[31]_i_12_n_0 ),
        .O(\result[7]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \result[7]_i_4 
       (.I0(load_data[7]),
        .I1(\state_reg_n_0_[1] ),
        .I2(OUT1[7]),
        .I3(\state_reg_n_0_[2] ),
        .O(\result[7]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \result[7]_i_5 
       (.I0(\result[7]_i_8_n_0 ),
        .I1(store_data[1]),
        .I2(\result[9]_i_7_n_0 ),
        .O(\result[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[7]_i_6 
       (.I0(store_data[7]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[7]_i_9_n_4 ),
        .I4(opcode_2[2]),
        .I5(\read_input[7]_i_1_n_0 ),
        .O(\result[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[7]_i_7 
       (.I0(data2[7]),
        .I1(opcode_2[3]),
        .I2(data5[7]),
        .I3(opcode_2[2]),
        .I4(\result_reg[7]_i_11_n_4 ),
        .I5(opcode_2[1]),
        .O(\result[7]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00000B08)) 
    \result[7]_i_8 
       (.I0(\read_input[0]_i_1_n_0 ),
        .I1(store_data[2]),
        .I2(store_data[4]),
        .I3(\read_input[4]_i_1_n_0 ),
        .I4(store_data[3]),
        .O(\result[7]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[8]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[8]),
        .I3(\result[8]_i_2_n_0 ),
        .I4(\result[8]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \result[8]_i_2 
       (.I0(\result[9]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[8]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[8]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAEAAAEAFFFFAAEA)) 
    \result[8]_i_3 
       (.I0(\result[8]_i_6_n_0 ),
        .I1(store_data[8]),
        .I2(\read_input[8]_i_1_n_0 ),
        .I3(\result[31]_i_12_n_0 ),
        .I4(data7[24]),
        .I5(\result[14]_i_7_n_0 ),
        .O(\result[8]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \result[8]_i_4 
       (.I0(\result[8]_i_7_n_0 ),
        .I1(store_data[1]),
        .I2(\result[10]_i_7_n_0 ),
        .O(\result[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[8]_i_5 
       (.I0(store_data[8]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[11]_i_8_n_7 ),
        .I4(opcode_2[2]),
        .I5(\read_input[8]_i_1_n_0 ),
        .O(\result[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[8]_i_6 
       (.I0(data2[8]),
        .I1(opcode_2[3]),
        .I2(data5[8]),
        .I3(opcode_2[2]),
        .I4(\result_reg[15]_i_16_n_7 ),
        .I5(opcode_2[1]),
        .O(\result[8]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h00000B08)) 
    \result[8]_i_7 
       (.I0(\read_input[1]_i_1_n_0 ),
        .I1(store_data[2]),
        .I2(store_data[4]),
        .I3(\read_input[5]_i_1_n_0 ),
        .I4(store_data[3]),
        .O(\result[8]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF20FF20202020)) 
    \result[9]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(load_data[9]),
        .I3(\result[9]_i_2_n_0 ),
        .I4(\result[9]_i_3_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\result[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF470000FFFFFFFF)) 
    \result[9]_i_2 
       (.I0(\result[9]_i_4_n_0 ),
        .I1(store_data[0]),
        .I2(\result[10]_i_4_n_0 ),
        .I3(\result[27]_i_8_n_0 ),
        .I4(\result[9]_i_5_n_0 ),
        .I5(opcode_2[0]),
        .O(\result[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAEAAAEAFFFFAAEA)) 
    \result[9]_i_3 
       (.I0(\result[9]_i_6_n_0 ),
        .I1(store_data[9]),
        .I2(\read_input[9]_i_1_n_0 ),
        .I3(\result[31]_i_12_n_0 ),
        .I4(data7[25]),
        .I5(\result[14]_i_7_n_0 ),
        .O(\result[9]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \result[9]_i_4 
       (.I0(\result[9]_i_7_n_0 ),
        .I1(store_data[1]),
        .I2(\result[11]_i_7_n_0 ),
        .O(\result[9]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h3030FCFF7777FCFF)) 
    \result[9]_i_5 
       (.I0(store_data[9]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\result_reg[11]_i_8_n_6 ),
        .I4(opcode_2[2]),
        .I5(\read_input[9]_i_1_n_0 ),
        .O(\result[9]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h33E200E200000000)) 
    \result[9]_i_6 
       (.I0(data2[9]),
        .I1(opcode_2[3]),
        .I2(data5[9]),
        .I3(opcode_2[2]),
        .I4(\result_reg[15]_i_16_n_6 ),
        .I5(opcode_2[1]),
        .O(\result[9]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h00000B08)) 
    \result[9]_i_7 
       (.I0(\read_input[2]_i_1_n_0 ),
        .I1(store_data[2]),
        .I2(store_data[4]),
        .I3(\read_input[6]_i_1_n_0 ),
        .I4(store_data[3]),
        .O(\result[9]_i_7_n_0 ));
  FDRE \result_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[0]_i_1_n_0 ),
        .Q(result[0]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[0]_i_10 
       (.CI(\result_reg[0]_i_23_n_0 ),
        .CO({data12,\NLW_result_reg[0]_i_10_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_24_n_0 ,\result[0]_i_16_n_0 ,\result[0]_i_17_n_0 ,\result[0]_i_18_n_0 }),
        .O(\NLW_result_reg[0]_i_10_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_25_n_0 ,\result[0]_i_26_n_0 ,\result[0]_i_27_n_0 ,\result[0]_i_28_n_0 }));
  CARRY4 \result_reg[0]_i_12 
       (.CI(\result_reg[0]_i_29_n_0 ),
        .CO({\NLW_result_reg[0]_i_12_CO_UNCONNECTED [3],data4,\NLW_result_reg[0]_i_12_CO_UNCONNECTED [1:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_result_reg[0]_i_12_O_UNCONNECTED [3:0]),
        .S({1'b0,\result[0]_i_30_n_0 ,\result[0]_i_31_n_0 ,\result[0]_i_32_n_0 }));
  CARRY4 \result_reg[0]_i_13 
       (.CI(\result_reg[0]_i_33_n_0 ),
        .CO({data6,\NLW_result_reg[0]_i_13_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_24_n_0 ,\result[0]_i_16_n_0 ,\result[0]_i_17_n_0 ,\result[0]_i_18_n_0 }),
        .O(\NLW_result_reg[0]_i_13_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_34_n_0 ,\result[0]_i_35_n_0 ,\result[0]_i_36_n_0 ,\result[0]_i_37_n_0 }));
  CARRY4 \result_reg[0]_i_14 
       (.CI(\result_reg[0]_i_38_n_0 ),
        .CO({\result_reg[0]_i_14_n_0 ,\NLW_result_reg[0]_i_14_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_39_n_0 ,\result[0]_i_40_n_0 ,\result[0]_i_41_n_0 ,\result[0]_i_42_n_0 }),
        .O(\NLW_result_reg[0]_i_14_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_43_n_0 ,\result[0]_i_44_n_0 ,\result[0]_i_45_n_0 ,\result[0]_i_46_n_0 }));
  CARRY4 \result_reg[0]_i_23 
       (.CI(\result_reg[0]_i_52_n_0 ),
        .CO({\result_reg[0]_i_23_n_0 ,\NLW_result_reg[0]_i_23_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_39_n_0 ,\result[0]_i_40_n_0 ,\result[0]_i_41_n_0 ,\result[0]_i_42_n_0 }),
        .O(\NLW_result_reg[0]_i_23_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_53_n_0 ,\result[0]_i_54_n_0 ,\result[0]_i_55_n_0 ,\result[0]_i_56_n_0 }));
  CARRY4 \result_reg[0]_i_29 
       (.CI(\result_reg[0]_i_57_n_0 ),
        .CO({\result_reg[0]_i_29_n_0 ,\NLW_result_reg[0]_i_29_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_result_reg[0]_i_29_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_58_n_0 ,\result[0]_i_59_n_0 ,\result[0]_i_60_n_0 ,\result[0]_i_61_n_0 }));
  CARRY4 \result_reg[0]_i_33 
       (.CI(\result_reg[0]_i_64_n_0 ),
        .CO({\result_reg[0]_i_33_n_0 ,\NLW_result_reg[0]_i_33_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_39_n_0 ,\result[0]_i_40_n_0 ,\result[0]_i_41_n_0 ,\result[0]_i_42_n_0 }),
        .O(\NLW_result_reg[0]_i_33_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_65_n_0 ,\result[0]_i_66_n_0 ,\result[0]_i_67_n_0 ,\result[0]_i_68_n_0 }));
  CARRY4 \result_reg[0]_i_38 
       (.CI(\result_reg[0]_i_69_n_0 ),
        .CO({\result_reg[0]_i_38_n_0 ,\NLW_result_reg[0]_i_38_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_70_n_0 ,\result[0]_i_71_n_0 ,\result[0]_i_72_n_0 ,\result[0]_i_73_n_0 }),
        .O(\NLW_result_reg[0]_i_38_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_74_n_0 ,\result[0]_i_75_n_0 ,\result[0]_i_76_n_0 ,\result[0]_i_77_n_0 }));
  CARRY4 \result_reg[0]_i_52 
       (.CI(\result_reg[0]_i_82_n_0 ),
        .CO({\result_reg[0]_i_52_n_0 ,\NLW_result_reg[0]_i_52_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_70_n_0 ,\result[0]_i_71_n_0 ,\result[0]_i_72_n_0 ,\result[0]_i_73_n_0 }),
        .O(\NLW_result_reg[0]_i_52_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_83_n_0 ,\result[0]_i_84_n_0 ,\result[0]_i_85_n_0 ,\result[0]_i_86_n_0 }));
  CARRY4 \result_reg[0]_i_57 
       (.CI(1'b0),
        .CO({\result_reg[0]_i_57_n_0 ,\NLW_result_reg[0]_i_57_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_result_reg[0]_i_57_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_87_n_0 ,\result[0]_i_88_n_0 ,\result[0]_i_89_n_0 ,\result[0]_i_90_n_0 }));
  CARRY4 \result_reg[0]_i_64 
       (.CI(\result_reg[0]_i_95_n_0 ),
        .CO({\result_reg[0]_i_64_n_0 ,\NLW_result_reg[0]_i_64_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_70_n_0 ,\result[0]_i_71_n_0 ,\result[0]_i_72_n_0 ,\result[0]_i_73_n_0 }),
        .O(\NLW_result_reg[0]_i_64_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_96_n_0 ,\result[0]_i_97_n_0 ,\result[0]_i_98_n_0 ,\result[0]_i_99_n_0 }));
  CARRY4 \result_reg[0]_i_69 
       (.CI(1'b0),
        .CO({\result_reg[0]_i_69_n_0 ,\NLW_result_reg[0]_i_69_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b1),
        .DI({\result[0]_i_100_n_0 ,\result[0]_i_101_n_0 ,\result[0]_i_102_n_0 ,\result[0]_i_103_n_0 }),
        .O(\NLW_result_reg[0]_i_69_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_104_n_0 ,\result[0]_i_105_n_0 ,\result[0]_i_106_n_0 ,\result[0]_i_107_n_0 }));
  CARRY4 \result_reg[0]_i_7 
       (.CI(\result_reg[0]_i_14_n_0 ),
        .CO({data10,\NLW_result_reg[0]_i_7_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_15_n_0 ,\result[0]_i_16_n_0 ,\result[0]_i_17_n_0 ,\result[0]_i_18_n_0 }),
        .O(\NLW_result_reg[0]_i_7_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_19_n_0 ,\result[0]_i_20_n_0 ,\result[0]_i_21_n_0 ,\result[0]_i_22_n_0 }));
  CARRY4 \result_reg[0]_i_82 
       (.CI(1'b0),
        .CO({\result_reg[0]_i_82_n_0 ,\NLW_result_reg[0]_i_82_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b1),
        .DI({\result[0]_i_100_n_0 ,\result[0]_i_101_n_0 ,\result[0]_i_102_n_0 ,\result[0]_i_103_n_0 }),
        .O(\NLW_result_reg[0]_i_82_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_110_n_0 ,\result[0]_i_111_n_0 ,\result[0]_i_112_n_0 ,\result[0]_i_113_n_0 }));
  CARRY4 \result_reg[0]_i_95 
       (.CI(1'b0),
        .CO({\result_reg[0]_i_95_n_0 ,\NLW_result_reg[0]_i_95_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\result[0]_i_100_n_0 ,\result[0]_i_101_n_0 ,\result[0]_i_102_n_0 ,\result[0]_i_103_n_0 }),
        .O(\NLW_result_reg[0]_i_95_O_UNCONNECTED [3:0]),
        .S({\result[0]_i_117_n_0 ,\result[0]_i_118_n_0 ,\result[0]_i_119_n_0 ,\result[0]_i_120_n_0 }));
  FDRE \result_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[10]_i_1_n_0 ),
        .Q(result[10]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[11]_i_1_n_0 ),
        .Q(result[11]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[11]_i_8 
       (.CI(\result_reg[7]_i_9_n_0 ),
        .CO({\result_reg[11]_i_8_n_0 ,\NLW_result_reg[11]_i_8_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
        .O({\result_reg[11]_i_8_n_4 ,\result_reg[11]_i_8_n_5 ,\result_reg[11]_i_8_n_6 ,\result_reg[11]_i_8_n_7 }),
        .S({\result[11]_i_9_n_0 ,\result[11]_i_10_n_0 ,\result[11]_i_11_n_0 ,\result[11]_i_12_n_0 }));
  FDRE \result_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[12]_i_1_n_0 ),
        .Q(result[12]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[13] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[13]_i_1_n_0 ),
        .Q(result[13]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[14] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[14]_i_1_n_0 ),
        .Q(result[14]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[15] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[15]_i_1_n_0 ),
        .Q(result[15]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[15]_i_10 
       (.CI(\result_reg[11]_i_8_n_0 ),
        .CO({\result_reg[15]_i_10_n_0 ,\NLW_result_reg[15]_i_10_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
        .O({\result_reg[15]_i_10_n_4 ,\result_reg[15]_i_10_n_5 ,\result_reg[15]_i_10_n_6 ,\result_reg[15]_i_10_n_7 }),
        .S({\result[15]_i_21_n_0 ,\result[15]_i_22_n_0 ,\result[15]_i_23_n_0 ,\result[15]_i_24_n_0 }));
  CARRY4 \result_reg[15]_i_11 
       (.CI(\result_reg[7]_i_10_n_0 ),
        .CO({\result_reg[15]_i_11_n_0 ,\NLW_result_reg[15]_i_11_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
        .O(data5[11:8]),
        .S({\result[15]_i_25_n_0 ,\result[15]_i_26_n_0 ,\result[15]_i_27_n_0 ,\result[15]_i_28_n_0 }));
  CARRY4 \result_reg[15]_i_16 
       (.CI(\result_reg[7]_i_11_n_0 ),
        .CO({\result_reg[15]_i_16_n_0 ,\NLW_result_reg[15]_i_16_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
        .O({\result_reg[15]_i_16_n_4 ,\result_reg[15]_i_16_n_5 ,\result_reg[15]_i_16_n_6 ,\result_reg[15]_i_16_n_7 }),
        .S({\result[15]_i_29_n_0 ,\result[15]_i_30_n_0 ,\result[15]_i_31_n_0 ,\result[15]_i_32_n_0 }));
  CARRY4 \result_reg[15]_i_7 
       (.CI(\result_reg[15]_i_11_n_0 ),
        .CO({\result_reg[15]_i_7_n_0 ,\NLW_result_reg[15]_i_7_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
        .O(data5[15:12]),
        .S({\result[15]_i_12_n_0 ,\result[15]_i_13_n_0 ,\result[15]_i_14_n_0 ,\result[15]_i_15_n_0 }));
  CARRY4 \result_reg[15]_i_8 
       (.CI(\result_reg[15]_i_16_n_0 ),
        .CO({\result_reg[15]_i_8_n_0 ,\NLW_result_reg[15]_i_8_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
        .O({\result_reg[15]_i_8_n_4 ,\result_reg[15]_i_8_n_5 ,\result_reg[15]_i_8_n_6 ,\result_reg[15]_i_8_n_7 }),
        .S({\result[15]_i_17_n_0 ,\result[15]_i_18_n_0 ,\result[15]_i_19_n_0 ,\result[15]_i_20_n_0 }));
  FDRE \result_reg[16] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[16]_i_1_n_0 ),
        .Q(result[16]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[16]_i_10 
       (.CI(\result_reg[8]_i_8_n_0 ),
        .CO({\result_reg[16]_i_10_n_0 ,\NLW_result_reg[16]_i_10_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data2[12:9]),
        .S(program_counter_2[12:9]));
  CARRY4 \result_reg[16]_i_7 
       (.CI(\result_reg[16]_i_10_n_0 ),
        .CO({data2[16],\NLW_result_reg[16]_i_7_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_result_reg[16]_i_7_O_UNCONNECTED [3],data2[15:13]}),
        .S({1'b1,program_counter_2[15:13]}));
  FDRE \result_reg[17] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[17]_i_1_n_0 ),
        .Q(result[17]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[18] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[18]_i_1_n_0 ),
        .Q(result[18]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[19] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[19]_i_1_n_0 ),
        .Q(result[19]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[19]_i_11 
       (.CI(\result_reg[15]_i_10_n_0 ),
        .CO({\result_reg[19]_i_11_n_0 ,\NLW_result_reg[19]_i_11_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\result_reg[19]_i_11_n_4 ,\result_reg[19]_i_11_n_5 ,\result_reg[19]_i_11_n_6 ,\result_reg[19]_i_11_n_7 }),
        .S({\result[19]_i_20_n_0 ,\result[19]_i_21_n_0 ,\result[19]_i_22_n_0 ,\result[19]_i_23_n_0 }));
  CARRY4 \result_reg[19]_i_6 
       (.CI(\result_reg[15]_i_7_n_0 ),
        .CO({\result_reg[19]_i_6_n_0 ,\NLW_result_reg[19]_i_6_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[19]_i_1_n_0 ,\read_input[18]_i_1_n_0 ,\read_input[17]_i_1_n_0 ,\read_input[16]_i_1_n_0 }),
        .O(data5[19:16]),
        .S({\result[19]_i_12_n_0 ,\result[19]_i_13_n_0 ,\result[19]_i_14_n_0 ,\result[19]_i_15_n_0 }));
  CARRY4 \result_reg[19]_i_7 
       (.CI(\result_reg[15]_i_8_n_0 ),
        .CO({\result_reg[19]_i_7_n_0 ,\NLW_result_reg[19]_i_7_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[19]_i_1_n_0 ,\read_input[18]_i_1_n_0 ,\read_input[17]_i_1_n_0 ,\read_input[16]_i_1_n_0 }),
        .O({\result_reg[19]_i_7_n_4 ,\result_reg[19]_i_7_n_5 ,\result_reg[19]_i_7_n_6 ,\result_reg[19]_i_7_n_7 }),
        .S({\result[19]_i_16_n_0 ,\result[19]_i_17_n_0 ,\result[19]_i_18_n_0 ,\result[19]_i_19_n_0 }));
  FDRE \result_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[1]_i_1_n_0 ),
        .Q(result[1]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[1]_i_6 
       (.CI(1'b0),
        .CO({\result_reg[1]_i_6_n_0 ,\NLW_result_reg[1]_i_6_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
        .O({\result_reg[1]_i_6_n_4 ,\result_reg[1]_i_6_n_5 ,\result_reg[1]_i_6_n_6 ,\result_reg[1]_i_6_n_7 }),
        .S({\result[1]_i_10_n_0 ,\result[1]_i_11_n_0 ,\result[1]_i_12_n_0 ,\result[1]_i_13_n_0 }));
  FDRE \result_reg[20] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[20]_i_1_n_0 ),
        .Q(result[20]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[21] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[21]_i_1_n_0 ),
        .Q(result[21]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[22] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[22]_i_1_n_0 ),
        .Q(result[22]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[23] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[23]_i_1_n_0 ),
        .Q(result[23]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[23]_i_10 
       (.CI(\result_reg[19]_i_11_n_0 ),
        .CO({\result_reg[23]_i_10_n_0 ,\NLW_result_reg[23]_i_10_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\result_reg[23]_i_10_n_4 ,\result_reg[23]_i_10_n_5 ,\result_reg[23]_i_10_n_6 ,\result_reg[23]_i_10_n_7 }),
        .S({\result[23]_i_20_n_0 ,\result[23]_i_21_n_0 ,\result[23]_i_22_n_0 ,\result[23]_i_23_n_0 }));
  CARRY4 \result_reg[23]_i_7 
       (.CI(\result_reg[19]_i_7_n_0 ),
        .CO({\result_reg[23]_i_7_n_0 ,\NLW_result_reg[23]_i_7_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[23]_i_1_n_0 ,\read_input[22]_i_1_n_0 ,\read_input[21]_i_1_n_0 ,\read_input[20]_i_1_n_0 }),
        .O({\result_reg[23]_i_7_n_4 ,\result_reg[23]_i_7_n_5 ,\result_reg[23]_i_7_n_6 ,\result_reg[23]_i_7_n_7 }),
        .S({\result[23]_i_12_n_0 ,\result[23]_i_13_n_0 ,\result[23]_i_14_n_0 ,\result[23]_i_15_n_0 }));
  CARRY4 \result_reg[23]_i_8 
       (.CI(\result_reg[19]_i_6_n_0 ),
        .CO({\result_reg[23]_i_8_n_0 ,\NLW_result_reg[23]_i_8_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[23]_i_1_n_0 ,\read_input[22]_i_1_n_0 ,\read_input[21]_i_1_n_0 ,\read_input[20]_i_1_n_0 }),
        .O(data5[23:20]),
        .S({\result[23]_i_16_n_0 ,\result[23]_i_17_n_0 ,\result[23]_i_18_n_0 ,\result[23]_i_19_n_0 }));
  FDRE \result_reg[24] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[24]_i_1_n_0 ),
        .Q(result[24]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[25] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[25]_i_1_n_0 ),
        .Q(result[25]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[26] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[26]_i_1_n_0 ),
        .Q(result[26]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[27] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[27]_i_1_n_0 ),
        .Q(result[27]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[27]_i_10 
       (.CI(\result_reg[23]_i_7_n_0 ),
        .CO({\result_reg[27]_i_10_n_0 ,\NLW_result_reg[27]_i_10_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[27]_i_1_n_0 ,\read_input[26]_i_1_n_0 ,\read_input[25]_i_1_n_0 ,\read_input[24]_i_1_n_0 }),
        .O({\result_reg[27]_i_10_n_4 ,\result_reg[27]_i_10_n_5 ,\result_reg[27]_i_10_n_6 ,\result_reg[27]_i_10_n_7 }),
        .S({\result[27]_i_27_n_0 ,\result[27]_i_28_n_0 ,\result[27]_i_29_n_0 ,\result[27]_i_30_n_0 }));
  CARRY4 \result_reg[27]_i_11 
       (.CI(\result_reg[23]_i_8_n_0 ),
        .CO({\result_reg[27]_i_11_n_0 ,\NLW_result_reg[27]_i_11_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[27]_i_1_n_0 ,\read_input[26]_i_1_n_0 ,\read_input[25]_i_1_n_0 ,\read_input[24]_i_1_n_0 }),
        .O(data5[27:24]),
        .S({\result[27]_i_31_n_0 ,\result[27]_i_32_n_0 ,\result[27]_i_33_n_0 ,\result[27]_i_34_n_0 }));
  FDRE \result_reg[28] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[28]_i_1_n_0 ),
        .Q(result[28]),
        .R(INTERNAL_RST_reg));
  MUXF7 \result_reg[28]_i_3 
       (.I0(\result[28]_i_6_n_0 ),
        .I1(\result[28]_i_7_n_0 ),
        .O(\result_reg[28]_i_3_n_0 ),
        .S(\result_reg[31]_i_9_n_7 ));
  FDRE \result_reg[29] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[29]_i_1_n_0 ),
        .Q(result[29]),
        .R(INTERNAL_RST_reg));
  MUXF7 \result_reg[29]_i_3 
       (.I0(\result[29]_i_6_n_0 ),
        .I1(\result[29]_i_7_n_0 ),
        .O(\result_reg[29]_i_3_n_0 ),
        .S(\result_reg[31]_i_9_n_6 ));
  FDRE \result_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[2]_i_1_n_0 ),
        .Q(result[2]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[30] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[30]_i_1_n_0 ),
        .Q(result[30]),
        .R(INTERNAL_RST_reg));
  MUXF7 \result_reg[30]_i_3 
       (.I0(\result[30]_i_6_n_0 ),
        .I1(\result[30]_i_7_n_0 ),
        .O(\result_reg[30]_i_3_n_0 ),
        .S(\result_reg[31]_i_9_n_5 ));
  FDRE \result_reg[31] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[31]_i_2_n_0 ),
        .Q(result[31]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[31]_i_14 
       (.CI(\result_reg[27]_i_11_n_0 ),
        .CO(\NLW_result_reg[31]_i_14_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,\read_input[30]_i_1_n_0 ,\read_input[29]_i_1_n_0 ,\read_input[28]_i_1_n_0 }),
        .O(data5[31:28]),
        .S({\result[31]_i_25_n_0 ,\result[31]_i_26_n_0 ,\result[31]_i_27_n_0 ,\result[31]_i_28_n_0 }));
  CARRY4 \result_reg[31]_i_15 
       (.CI(\result_reg[27]_i_10_n_0 ),
        .CO(\NLW_result_reg[31]_i_15_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,\read_input[30]_i_1_n_0 ,\read_input[29]_i_1_n_0 ,\read_input[28]_i_1_n_0 }),
        .O({\result_reg[31]_i_15_n_4 ,\result_reg[31]_i_15_n_5 ,\result_reg[31]_i_15_n_6 ,\result_reg[31]_i_15_n_7 }),
        .S({\result[31]_i_29_n_0 ,\result[31]_i_30_n_0 ,\result[31]_i_31_n_0 ,\result[31]_i_32_n_0 }));
  CARRY4 \result_reg[31]_i_16 
       (.CI(\result_reg[23]_i_10_n_0 ),
        .CO({\result_reg[31]_i_16_n_0 ,\NLW_result_reg[31]_i_16_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\result_reg[31]_i_16_n_4 ,\result_reg[31]_i_16_n_5 ,\result_reg[31]_i_16_n_6 ,\result_reg[31]_i_16_n_7 }),
        .S({\result[31]_i_33_n_0 ,\result[31]_i_34_n_0 ,\result[31]_i_35_n_0 ,\result[31]_i_36_n_0 }));
  MUXF7 \result_reg[31]_i_6 
       (.I0(\result[31]_i_10_n_0 ),
        .I1(\result[31]_i_11_n_0 ),
        .O(\result_reg[31]_i_6_n_0 ),
        .S(\result_reg[31]_i_9_n_4 ));
  CARRY4 \result_reg[31]_i_9 
       (.CI(\result_reg[31]_i_16_n_0 ),
        .CO(\NLW_result_reg[31]_i_9_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\result_reg[31]_i_9_n_4 ,\result_reg[31]_i_9_n_5 ,\result_reg[31]_i_9_n_6 ,\result_reg[31]_i_9_n_7 }),
        .S({\result[31]_i_17_n_0 ,\result[31]_i_18_n_0 ,\result[31]_i_19_n_0 ,\result[31]_i_20_n_0 }));
  FDRE \result_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[3]_i_1_n_0 ),
        .Q(result[3]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[3]_i_8 
       (.CI(1'b0),
        .CO({\result_reg[3]_i_8_n_0 ,\NLW_result_reg[3]_i_8_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b1),
        .DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
        .O(data5[3:0]),
        .S({\result[3]_i_10_n_0 ,\result[3]_i_11_n_0 ,\result[3]_i_12_n_0 ,\result[3]_i_13_n_0 }));
  CARRY4 \result_reg[3]_i_9 
       (.CI(1'b0),
        .CO({\result_reg[3]_i_9_n_0 ,\NLW_result_reg[3]_i_9_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
        .O({\result_reg[3]_i_9_n_4 ,\result_reg[3]_i_9_n_5 ,\result_reg[3]_i_9_n_6 ,\result_reg[3]_i_9_n_7 }),
        .S({\result[3]_i_14_n_0 ,\result[3]_i_15_n_0 ,\result[3]_i_16_n_0 ,\result[3]_i_17_n_0 }));
  FDRE \result_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[4]_i_1_n_0 ),
        .Q(result[4]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[4]_i_8 
       (.CI(1'b0),
        .CO({\result_reg[4]_i_8_n_0 ,\NLW_result_reg[4]_i_8_CO_UNCONNECTED [2:0]}),
        .CYINIT(program_counter_2[0]),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data2[4:1]),
        .S(program_counter_2[4:1]));
  FDRE \result_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[5]_i_1_n_0 ),
        .Q(result[5]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[6]_i_1_n_0 ),
        .Q(result[6]),
        .R(INTERNAL_RST_reg));
  FDRE \result_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[7]_i_1_n_0 ),
        .Q(result[7]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[7]_i_10 
       (.CI(\result_reg[3]_i_8_n_0 ),
        .CO({\result_reg[7]_i_10_n_0 ,\NLW_result_reg[7]_i_10_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
        .O(data5[7:4]),
        .S({\result[7]_i_16_n_0 ,\result[7]_i_17_n_0 ,\result[7]_i_18_n_0 ,\result[7]_i_19_n_0 }));
  CARRY4 \result_reg[7]_i_11 
       (.CI(\result_reg[3]_i_9_n_0 ),
        .CO({\result_reg[7]_i_11_n_0 ,\NLW_result_reg[7]_i_11_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
        .O({\result_reg[7]_i_11_n_4 ,\result_reg[7]_i_11_n_5 ,\result_reg[7]_i_11_n_6 ,\result_reg[7]_i_11_n_7 }),
        .S({\result[7]_i_20_n_0 ,\result[7]_i_21_n_0 ,\result[7]_i_22_n_0 ,\result[7]_i_23_n_0 }));
  CARRY4 \result_reg[7]_i_9 
       (.CI(\result_reg[1]_i_6_n_0 ),
        .CO({\result_reg[7]_i_9_n_0 ,\NLW_result_reg[7]_i_9_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
        .O({\result_reg[7]_i_9_n_4 ,\result_reg[7]_i_9_n_5 ,\result_reg[7]_i_9_n_6 ,\result_reg[7]_i_9_n_7 }),
        .S({\result[7]_i_12_n_0 ,\result[7]_i_13_n_0 ,\result[7]_i_14_n_0 ,\result[7]_i_15_n_0 }));
  FDRE \result_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[8]_i_1_n_0 ),
        .Q(result[8]),
        .R(INTERNAL_RST_reg));
  CARRY4 \result_reg[8]_i_8 
       (.CI(\result_reg[4]_i_8_n_0 ),
        .CO({\result_reg[8]_i_8_n_0 ,\NLW_result_reg[8]_i_8_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data2[8:5]),
        .S(program_counter_2[8:5]));
  FDRE \result_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\result[31]_i_1_n_0 ),
        .D(\result[9]_i_1_n_0 ),
        .Q(result[9]),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'hFFFF7FFF0000C000)) 
    \s_input_rs232_in_ack[0]_i_1 
       (.I0(OUT1_STB),
        .I1(\s_input_rs232_in_ack[0]_i_2_n_0 ),
        .I2(\state_reg_n_0_[1] ),
        .I3(\state_reg_n_0_[2] ),
        .I4(\state_reg_n_0_[0] ),
        .I5(OUT1_ACK),
        .O(\s_input_rs232_in_ack[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \s_input_rs232_in_ack[0]_i_2 
       (.I0(\s_input_rs232_in_ack[0]_i_3_n_0 ),
        .I1(\s_input_rs232_in_ack[0]_i_4_n_0 ),
        .I2(\s_input_rs232_in_ack[0]_i_5_n_0 ),
        .I3(\s_input_rs232_in_ack[0]_i_6_n_0 ),
        .I4(\s_input_rs232_in_ack[0]_i_7_n_0 ),
        .I5(\s_input_rs232_in_ack[0]_i_8_n_0 ),
        .O(\s_input_rs232_in_ack[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \s_input_rs232_in_ack[0]_i_3 
       (.I0(read_input[12]),
        .I1(read_input[6]),
        .I2(read_input[4]),
        .I3(read_input[9]),
        .I4(read_input[17]),
        .I5(read_input[18]),
        .O(\s_input_rs232_in_ack[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \s_input_rs232_in_ack[0]_i_4 
       (.I0(read_input[8]),
        .I1(read_input[31]),
        .O(\s_input_rs232_in_ack[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \s_input_rs232_in_ack[0]_i_5 
       (.I0(read_input[11]),
        .I1(read_input[10]),
        .I2(read_input[14]),
        .I3(read_input[20]),
        .I4(read_input[7]),
        .I5(read_input[19]),
        .O(\s_input_rs232_in_ack[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \s_input_rs232_in_ack[0]_i_6 
       (.I0(read_input[29]),
        .I1(read_input[0]),
        .I2(read_input[26]),
        .I3(read_input[30]),
        .I4(read_input[13]),
        .I5(read_input[15]),
        .O(\s_input_rs232_in_ack[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \s_input_rs232_in_ack[0]_i_7 
       (.I0(read_input[24]),
        .I1(read_input[1]),
        .I2(read_input[2]),
        .I3(read_input[23]),
        .I4(read_input[3]),
        .I5(read_input[28]),
        .O(\s_input_rs232_in_ack[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \s_input_rs232_in_ack[0]_i_8 
       (.I0(read_input[27]),
        .I1(read_input[21]),
        .I2(read_input[16]),
        .I3(read_input[22]),
        .I4(read_input[5]),
        .I5(read_input[25]),
        .O(\s_input_rs232_in_ack[0]_i_8_n_0 ));
  FDRE \s_input_rs232_in_ack_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\s_input_rs232_in_ack[0]_i_1_n_0 ),
        .Q(OUT1_ACK),
        .R(INTERNAL_RST_reg));
  LUT3 #(
    .INIT(8'h80)) 
    \s_output_rs232_out[7]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(\s_output_rs232_out[7]_i_2_n_0 ),
        .O(\s_output_rs232_out[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \s_output_rs232_out[7]_i_2 
       (.I0(\s_output_rs232_out[7]_i_3_n_0 ),
        .I1(\s_output_rs232_out[7]_i_4_n_0 ),
        .I2(\s_output_rs232_out[7]_i_5_n_0 ),
        .I3(\s_output_rs232_out[7]_i_6_n_0 ),
        .I4(\s_output_rs232_out[7]_i_7_n_0 ),
        .I5(\s_output_rs232_out[7]_i_8_n_0 ),
        .O(\s_output_rs232_out[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \s_output_rs232_out[7]_i_3 
       (.I0(write_output[15]),
        .I1(write_output[12]),
        .I2(write_output[20]),
        .I3(write_output[21]),
        .I4(write_output[6]),
        .I5(write_output[23]),
        .O(\s_output_rs232_out[7]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \s_output_rs232_out[7]_i_4 
       (.I0(write_output[31]),
        .I1(write_output[27]),
        .I2(write_output[30]),
        .O(\s_output_rs232_out[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \s_output_rs232_out[7]_i_5 
       (.I0(write_output[8]),
        .I1(write_output[16]),
        .I2(write_output[26]),
        .I3(write_output[24]),
        .I4(write_output[10]),
        .I5(write_output[22]),
        .O(\s_output_rs232_out[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \s_output_rs232_out[7]_i_6 
       (.I0(write_output[13]),
        .I1(write_output[29]),
        .I2(\state_reg_n_0_[0] ),
        .I3(write_output[25]),
        .I4(write_output[18]),
        .I5(write_output[1]),
        .O(\s_output_rs232_out[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \s_output_rs232_out[7]_i_7 
       (.I0(write_output[11]),
        .I1(write_output[3]),
        .I2(write_output[5]),
        .I3(write_output[9]),
        .I4(write_output[7]),
        .I5(write_output[14]),
        .O(\s_output_rs232_out[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \s_output_rs232_out[7]_i_8 
       (.I0(write_output[19]),
        .I1(write_output[2]),
        .I2(write_output[0]),
        .I3(write_output[28]),
        .I4(write_output[4]),
        .I5(write_output[17]),
        .O(\s_output_rs232_out[7]_i_8_n_0 ));
  FDRE \s_output_rs232_out_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\s_output_rs232_out[7]_i_1_n_0 ),
        .D(write_value[0]),
        .Q(output_rs232_out[0]),
        .R(1'b0));
  FDRE \s_output_rs232_out_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\s_output_rs232_out[7]_i_1_n_0 ),
        .D(write_value[1]),
        .Q(output_rs232_out[1]),
        .R(1'b0));
  FDRE \s_output_rs232_out_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\s_output_rs232_out[7]_i_1_n_0 ),
        .D(write_value[2]),
        .Q(output_rs232_out[2]),
        .R(1'b0));
  FDRE \s_output_rs232_out_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\s_output_rs232_out[7]_i_1_n_0 ),
        .D(write_value[3]),
        .Q(output_rs232_out[3]),
        .R(1'b0));
  FDRE \s_output_rs232_out_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\s_output_rs232_out[7]_i_1_n_0 ),
        .D(write_value[4]),
        .Q(output_rs232_out[4]),
        .R(1'b0));
  FDRE \s_output_rs232_out_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\s_output_rs232_out[7]_i_1_n_0 ),
        .D(write_value[5]),
        .Q(output_rs232_out[5]),
        .R(1'b0));
  FDRE \s_output_rs232_out_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\s_output_rs232_out[7]_i_1_n_0 ),
        .D(write_value[6]),
        .Q(output_rs232_out[6]),
        .R(1'b0));
  FDRE \s_output_rs232_out_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\s_output_rs232_out[7]_i_1_n_0 ),
        .D(write_value[7]),
        .Q(output_rs232_out[7]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h7FFF8080)) 
    \s_output_rs232_out_stb[0]_i_1 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[1] ),
        .I2(\s_output_rs232_out[7]_i_2_n_0 ),
        .I3(IN1_ACK),
        .I4(IN1_STB),
        .O(\s_output_rs232_out_stb[0]_i_1_n_0 ));
  FDRE \s_output_rs232_out_stb_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\s_output_rs232_out_stb[0]_i_1_n_0 ),
        .Q(IN1_STB),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'hAAAAAEFFAAAAA200)) 
    \state[0]_i_1 
       (.I0(\state[0]_i_2_n_0 ),
        .I1(\state[2]_i_3_n_0 ),
        .I2(\state[2]_i_4_n_0 ),
        .I3(instruction0),
        .I4(\state[2]_i_5_n_0 ),
        .I5(\state_reg_n_0_[0] ),
        .O(\state[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hBF)) 
    \state[0]_i_2 
       (.I0(\state_reg_n_0_[2] ),
        .I1(\state_reg_n_0_[0] ),
        .I2(\state[0]_i_3_n_0 ),
        .O(\state[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFDFFFFDFDFD7FF7F)) 
    \state[0]_i_3 
       (.I0(\state_reg_n_0_[1] ),
        .I1(opcode_2[3]),
        .I2(opcode_2[1]),
        .I3(opcode_2[2]),
        .I4(opcode_2[0]),
        .I5(opcode_2[4]),
        .O(\state[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAEFFAAAAA200)) 
    \state[1]_i_1 
       (.I0(\state[1]_i_2_n_0 ),
        .I1(\state[2]_i_3_n_0 ),
        .I2(\state[2]_i_4_n_0 ),
        .I3(instruction0),
        .I4(\state[2]_i_5_n_0 ),
        .I5(\state_reg_n_0_[1] ),
        .O(\state[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0020FFFFFFFFFFFF)) 
    \state[1]_i_2 
       (.I0(opcode_2[4]),
        .I1(opcode_2[2]),
        .I2(opcode_2[1]),
        .I3(opcode_2[3]),
        .I4(\state_reg_n_0_[0] ),
        .I5(opcode_20),
        .O(\state[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAEFFAAAAA200)) 
    \state[2]_i_1 
       (.I0(\state[2]_i_2_n_0 ),
        .I1(\state[2]_i_3_n_0 ),
        .I2(\state[2]_i_4_n_0 ),
        .I3(instruction0),
        .I4(\state[2]_i_5_n_0 ),
        .I5(\state_reg_n_0_[2] ),
        .O(\state[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000C002000000000)) 
    \state[2]_i_2 
       (.I0(opcode_2[0]),
        .I1(opcode_2[1]),
        .I2(opcode_2[2]),
        .I3(opcode_2[3]),
        .I4(opcode_2[4]),
        .I5(\address_z_3[3]_i_1_n_0 ),
        .O(\state[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBABFBEFEBEBFBEF)) 
    \state[2]_i_3 
       (.I0(opcode_2[3]),
        .I1(opcode_2[1]),
        .I2(opcode_2[2]),
        .I3(opcode_2[4]),
        .I4(opcode_2[0]),
        .I5(\program_counter[15]_i_8_n_0 ),
        .O(\state[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0006FFFFFFFFFFFF)) 
    \state[2]_i_4 
       (.I0(opcode_2[0]),
        .I1(opcode_2[1]),
        .I2(opcode_2[4]),
        .I3(\state[2]_i_6_n_0 ),
        .I4(\state_reg_n_0_[1] ),
        .I5(\state_reg_n_0_[0] ),
        .O(\state[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hF444444444444444)) 
    \state[2]_i_5 
       (.I0(\program_counter[15]_i_15_n_0 ),
        .I1(\result[31]_i_4_n_0 ),
        .I2(IN1_ACK),
        .I3(IN1_STB),
        .I4(\state_reg_n_0_[2] ),
        .I5(\s_output_rs232_out[7]_i_2_n_0 ),
        .O(\state[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \state[2]_i_6 
       (.I0(opcode_2[2]),
        .I1(opcode_2[3]),
        .O(\state[2]_i_6_n_0 ));
  FDSE \state_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\state[0]_i_1_n_0 ),
        .Q(\state_reg_n_0_[0] ),
        .S(INTERNAL_RST_reg));
  FDRE \state_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\state[1]_i_1_n_0 ),
        .Q(\state_reg_n_0_[1] ),
        .R(INTERNAL_RST_reg));
  FDRE \state_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\state[2]_i_1_n_0 ),
        .Q(\state_reg_n_0_[2] ),
        .R(INTERNAL_RST_reg));
  FDRE write_enable_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\result[31]_i_1_n_0 ),
        .Q(write_enable_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000080000)) 
    \write_output[31]_i_1 
       (.I0(opcode_2[4]),
        .I1(\address_z_3[3]_i_1_n_0 ),
        .I2(opcode_2[0]),
        .I3(opcode_2[2]),
        .I4(opcode_2[1]),
        .I5(opcode_2[3]),
        .O(out0));
  FDRE \write_output_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[0]_i_1_n_0 ),
        .Q(write_output[0]),
        .R(1'b0));
  FDRE \write_output_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[10]_i_1_n_0 ),
        .Q(write_output[10]),
        .R(1'b0));
  FDRE \write_output_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[11]_i_1_n_0 ),
        .Q(write_output[11]),
        .R(1'b0));
  FDRE \write_output_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[12]_i_1_n_0 ),
        .Q(write_output[12]),
        .R(1'b0));
  FDRE \write_output_reg[13] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[13]_i_1_n_0 ),
        .Q(write_output[13]),
        .R(1'b0));
  FDRE \write_output_reg[14] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[14]_i_1_n_0 ),
        .Q(write_output[14]),
        .R(1'b0));
  FDRE \write_output_reg[15] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[15]_i_1_n_0 ),
        .Q(write_output[15]),
        .R(1'b0));
  FDRE \write_output_reg[16] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[16]_i_1_n_0 ),
        .Q(write_output[16]),
        .R(1'b0));
  FDRE \write_output_reg[17] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[17]_i_1_n_0 ),
        .Q(write_output[17]),
        .R(1'b0));
  FDRE \write_output_reg[18] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[18]_i_1_n_0 ),
        .Q(write_output[18]),
        .R(1'b0));
  FDRE \write_output_reg[19] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[19]_i_1_n_0 ),
        .Q(write_output[19]),
        .R(1'b0));
  FDRE \write_output_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[1]_i_1_n_0 ),
        .Q(write_output[1]),
        .R(1'b0));
  FDRE \write_output_reg[20] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[20]_i_1_n_0 ),
        .Q(write_output[20]),
        .R(1'b0));
  FDRE \write_output_reg[21] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[21]_i_1_n_0 ),
        .Q(write_output[21]),
        .R(1'b0));
  FDRE \write_output_reg[22] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[22]_i_1_n_0 ),
        .Q(write_output[22]),
        .R(1'b0));
  FDRE \write_output_reg[23] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[23]_i_1_n_0 ),
        .Q(write_output[23]),
        .R(1'b0));
  FDRE \write_output_reg[24] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[24]_i_1_n_0 ),
        .Q(write_output[24]),
        .R(1'b0));
  FDRE \write_output_reg[25] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[25]_i_1_n_0 ),
        .Q(write_output[25]),
        .R(1'b0));
  FDRE \write_output_reg[26] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[26]_i_1_n_0 ),
        .Q(write_output[26]),
        .R(1'b0));
  FDRE \write_output_reg[27] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[27]_i_1_n_0 ),
        .Q(write_output[27]),
        .R(1'b0));
  FDRE \write_output_reg[28] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[28]_i_1_n_0 ),
        .Q(write_output[28]),
        .R(1'b0));
  FDRE \write_output_reg[29] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[29]_i_1_n_0 ),
        .Q(write_output[29]),
        .R(1'b0));
  FDRE \write_output_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[2]_i_1_n_0 ),
        .Q(write_output[2]),
        .R(1'b0));
  FDRE \write_output_reg[30] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[30]_i_1_n_0 ),
        .Q(write_output[30]),
        .R(1'b0));
  FDRE \write_output_reg[31] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[31]_i_2_n_0 ),
        .Q(write_output[31]),
        .R(1'b0));
  FDRE \write_output_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[3]_i_1_n_0 ),
        .Q(write_output[3]),
        .R(1'b0));
  FDRE \write_output_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[4]_i_1_n_0 ),
        .Q(write_output[4]),
        .R(1'b0));
  FDRE \write_output_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[5]_i_1_n_0 ),
        .Q(write_output[5]),
        .R(1'b0));
  FDRE \write_output_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[6]_i_1_n_0 ),
        .Q(write_output[6]),
        .R(1'b0));
  FDRE \write_output_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[7]_i_1_n_0 ),
        .Q(write_output[7]),
        .R(1'b0));
  FDRE \write_output_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[8]_i_1_n_0 ),
        .Q(write_output[8]),
        .R(1'b0));
  FDRE \write_output_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(\read_input[9]_i_1_n_0 ),
        .Q(write_output[9]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_value[0]_i_1 
       (.I0(result[0]),
        .I1(operand_b1),
        .I2(register_b[0]),
        .O(store_data[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_value[1]_i_1 
       (.I0(result[1]),
        .I1(operand_b1),
        .I2(register_b[1]),
        .O(store_data[1]));
  LUT6 #(
    .INIT(64'h2002000000002002)) 
    \write_value[1]_i_2 
       (.I0(write_enable_reg_n_0),
        .I1(\write_value[7]_i_2_n_0 ),
        .I2(address_z_3[0]),
        .I3(address_b_2[0]),
        .I4(address_z_3[3]),
        .I5(address_b_2[3]),
        .O(operand_b1));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \write_value[2]_i_1 
       (.I0(result[2]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[2]),
        .O(store_data[2]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \write_value[3]_i_1 
       (.I0(result[3]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[3]),
        .O(store_data[3]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \write_value[4]_i_1 
       (.I0(result[4]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[4]),
        .O(store_data[4]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \write_value[5]_i_1 
       (.I0(result[5]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[5]),
        .O(store_data[5]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \write_value[6]_i_1 
       (.I0(result[6]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[6]),
        .O(store_data[6]));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    \write_value[7]_i_1 
       (.I0(result[7]),
        .I1(write_enable_reg_n_0),
        .I2(\write_value[7]_i_2_n_0 ),
        .I3(\write_value[7]_i_3_n_0 ),
        .I4(register_b[7]),
        .O(store_data[7]));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \write_value[7]_i_2 
       (.I0(address_z_3[2]),
        .I1(address_b_2[2]),
        .I2(address_z_3[1]),
        .I3(address_b_2[1]),
        .O(\write_value[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \write_value[7]_i_3 
       (.I0(address_z_3[0]),
        .I1(address_b_2[0]),
        .I2(address_z_3[3]),
        .I3(address_b_2[3]),
        .O(\write_value[7]_i_3_n_0 ));
  FDRE \write_value_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(store_data[0]),
        .Q(write_value[0]),
        .R(1'b0));
  FDRE \write_value_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(store_data[1]),
        .Q(write_value[1]),
        .R(1'b0));
  FDRE \write_value_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(store_data[2]),
        .Q(write_value[2]),
        .R(1'b0));
  FDRE \write_value_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(store_data[3]),
        .Q(write_value[3]),
        .R(1'b0));
  FDRE \write_value_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(store_data[4]),
        .Q(write_value[4]),
        .R(1'b0));
  FDRE \write_value_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(store_data[5]),
        .Q(write_value[5]),
        .R(1'b0));
  FDRE \write_value_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(store_data[6]),
        .Q(write_value[6]),
        .R(1'b0));
  FDRE \write_value_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(out0),
        .D(store_data[7]),
        .Q(write_value[7]),
        .R(1'b0));
endmodule

module pwm_audio
   (JC_IBUF,
    INTERNAL_RST_reg,
    ETH_CLK_OBUF);
  output [0:0]JC_IBUF;
  input INTERNAL_RST_reg;
  input ETH_CLK_OBUF;

  wire \COUNT[10]_i_2_n_0 ;
  wire \COUNT[10]_i_4_n_0 ;
  wire \COUNT[10]_i_5_n_0 ;
  wire \COUNT[10]_i_6_n_0 ;
  wire \COUNT[9]_i_2_n_0 ;
  wire [10:0]COUNT_reg__0;
  wire ETH_CLK_OBUF;
  wire INTERNAL_RST_reg;
  wire [0:0]JC_IBUF;
  wire STATE;
  wire STATE_i_1_n_0;
  wire STATE_reg_n_0;
  wire S_DATA_IN_ACK_i_1_n_0;
  wire [10:0]p_0_in;

  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \COUNT[0]_i_1__4 
       (.I0(COUNT_reg__0[0]),
        .O(p_0_in[0]));
  LUT2 #(
    .INIT(4'h2)) 
    \COUNT[10]_i_1 
       (.I0(JC_IBUF),
        .I1(STATE_reg_n_0),
        .O(STATE));
  LUT2 #(
    .INIT(4'h2)) 
    \COUNT[10]_i_2 
       (.I0(STATE_reg_n_0),
        .I1(\COUNT[10]_i_4_n_0 ),
        .O(\COUNT[10]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \COUNT[10]_i_3 
       (.I0(COUNT_reg__0[10]),
        .I1(\COUNT[10]_i_5_n_0 ),
        .I2(COUNT_reg__0[9]),
        .O(p_0_in[10]));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    \COUNT[10]_i_4 
       (.I0(COUNT_reg__0[2]),
        .I1(COUNT_reg__0[3]),
        .I2(COUNT_reg__0[6]),
        .I3(COUNT_reg__0[5]),
        .I4(COUNT_reg__0[7]),
        .I5(\COUNT[10]_i_6_n_0 ),
        .O(\COUNT[10]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \COUNT[10]_i_5 
       (.I0(COUNT_reg__0[8]),
        .I1(COUNT_reg__0[7]),
        .I2(\COUNT[9]_i_2_n_0 ),
        .I3(COUNT_reg__0[6]),
        .I4(COUNT_reg__0[5]),
        .O(\COUNT[10]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \COUNT[10]_i_6 
       (.I0(COUNT_reg__0[9]),
        .I1(COUNT_reg__0[10]),
        .I2(COUNT_reg__0[4]),
        .I3(COUNT_reg__0[8]),
        .I4(COUNT_reg__0[0]),
        .I5(COUNT_reg__0[1]),
        .O(\COUNT[10]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \COUNT[1]_i_1__4 
       (.I0(COUNT_reg__0[0]),
        .I1(COUNT_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \COUNT[2]_i_1__3 
       (.I0(COUNT_reg__0[0]),
        .I1(COUNT_reg__0[1]),
        .I2(COUNT_reg__0[2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \COUNT[3]_i_1__2 
       (.I0(COUNT_reg__0[3]),
        .I1(COUNT_reg__0[0]),
        .I2(COUNT_reg__0[1]),
        .I3(COUNT_reg__0[2]),
        .O(p_0_in[3]));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \COUNT[4]_i_1__2 
       (.I0(COUNT_reg__0[1]),
        .I1(COUNT_reg__0[0]),
        .I2(COUNT_reg__0[3]),
        .I3(COUNT_reg__0[2]),
        .I4(COUNT_reg__0[4]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \COUNT[5]_i_1__2 
       (.I0(COUNT_reg__0[5]),
        .I1(COUNT_reg__0[1]),
        .I2(COUNT_reg__0[0]),
        .I3(COUNT_reg__0[3]),
        .I4(COUNT_reg__0[2]),
        .I5(COUNT_reg__0[4]),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \COUNT[6]_i_1__2 
       (.I0(COUNT_reg__0[6]),
        .I1(\COUNT[9]_i_2_n_0 ),
        .I2(COUNT_reg__0[5]),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \COUNT[7]_i_1__2 
       (.I0(COUNT_reg__0[7]),
        .I1(COUNT_reg__0[5]),
        .I2(COUNT_reg__0[6]),
        .I3(\COUNT[9]_i_2_n_0 ),
        .O(p_0_in[7]));
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \COUNT[8]_i_1 
       (.I0(COUNT_reg__0[8]),
        .I1(COUNT_reg__0[7]),
        .I2(\COUNT[9]_i_2_n_0 ),
        .I3(COUNT_reg__0[6]),
        .I4(COUNT_reg__0[5]),
        .O(p_0_in[8]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \COUNT[9]_i_1 
       (.I0(COUNT_reg__0[9]),
        .I1(COUNT_reg__0[5]),
        .I2(COUNT_reg__0[6]),
        .I3(\COUNT[9]_i_2_n_0 ),
        .I4(COUNT_reg__0[7]),
        .I5(COUNT_reg__0[8]),
        .O(p_0_in[9]));
  LUT5 #(
    .INIT(32'h80000000)) 
    \COUNT[9]_i_2 
       (.I0(COUNT_reg__0[4]),
        .I1(COUNT_reg__0[2]),
        .I2(COUNT_reg__0[3]),
        .I3(COUNT_reg__0[0]),
        .I4(COUNT_reg__0[1]),
        .O(\COUNT[9]_i_2_n_0 ));
  FDRE \COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[0]),
        .Q(COUNT_reg__0[0]),
        .R(STATE));
  FDRE \COUNT_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[10]),
        .Q(COUNT_reg__0[10]),
        .R(STATE));
  FDRE \COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[1]),
        .Q(COUNT_reg__0[1]),
        .R(STATE));
  FDRE \COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[2]),
        .Q(COUNT_reg__0[2]),
        .R(STATE));
  FDRE \COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[3]),
        .Q(COUNT_reg__0[3]),
        .R(STATE));
  FDRE \COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[4]),
        .Q(COUNT_reg__0[4]),
        .R(STATE));
  FDRE \COUNT_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[5]),
        .Q(COUNT_reg__0[5]),
        .R(STATE));
  FDRE \COUNT_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[6]),
        .Q(COUNT_reg__0[6]),
        .R(STATE));
  FDRE \COUNT_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[7]),
        .Q(COUNT_reg__0[7]),
        .R(STATE));
  FDRE \COUNT_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[8]),
        .Q(COUNT_reg__0[8]),
        .R(STATE));
  FDRE \COUNT_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\COUNT[10]_i_2_n_0 ),
        .D(p_0_in[9]),
        .Q(COUNT_reg__0[9]),
        .R(STATE));
  LUT3 #(
    .INIT(8'h4E)) 
    STATE_i_1
       (.I0(STATE_reg_n_0),
        .I1(JC_IBUF),
        .I2(\COUNT[10]_i_4_n_0 ),
        .O(STATE_i_1_n_0));
  FDRE STATE_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(STATE_i_1_n_0),
        .Q(STATE_reg_n_0),
        .R(INTERNAL_RST_reg));
  LUT3 #(
    .INIT(8'h09)) 
    S_DATA_IN_ACK_i_1
       (.I0(STATE_reg_n_0),
        .I1(JC_IBUF),
        .I2(INTERNAL_RST_reg),
        .O(S_DATA_IN_ACK_i_1_n_0));
  FDRE S_DATA_IN_ACK_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(S_DATA_IN_ACK_i_1_n_0),
        .Q(JC_IBUF),
        .R(1'b0));
endmodule

module rmii_ethernet
   (TXEN_OBUF,
    TXD_OBUF,
    ETH_CLK_OBUF,
    RXDV_IBUF,
    RXER_IBUF,
    INTERNAL_RST_reg,
    D);
  output TXEN_OBUF;
  output [1:0]TXD_OBUF;
  input ETH_CLK_OBUF;
  input RXDV_IBUF;
  input RXER_IBUF;
  input INTERNAL_RST_reg;
  input [1:0]D;

  wire DONE;
  wire DONE_DEL;
  wire DONE_SYNC;
  wire DONE_i_1_n_0;
  wire ETH_CLK_OBUF;
  wire GO;
  wire GO_DEL;
  wire GO_SYNC;
  wire GO_i_1_n_0;
  wire INTERNAL_RST_reg;
  wire NEXTCRC32_D80177_out;
  wire NEXTCRC32_D80181_out;
  wire NEXTCRC32_D80189_out;
  wire NEXTCRC32_D80195_out;
  wire NEXTCRC32_D80203_out;
  wire NEXTCRC32_D80217_out;
  wire NEXTCRC32_D8070_out;
  wire NEXTCRC32_D8074_out;
  wire \PREAMBLE_COUNT[0]_i_1_n_0 ;
  wire \PREAMBLE_COUNT[1]_i_1_n_0 ;
  wire \PREAMBLE_COUNT[2]_i_1_n_0 ;
  wire \PREAMBLE_COUNT[3]_i_1_n_0 ;
  wire \PREAMBLE_COUNT[4]_i_1_n_0 ;
  wire \PREAMBLE_COUNT[4]_i_2_n_0 ;
  wire \PREAMBLE_COUNT[4]_i_3_n_0 ;
  wire \PREAMBLE_COUNT[4]_i_4_n_0 ;
  wire \PREAMBLE_COUNT_reg_n_0_[0] ;
  wire \PREAMBLE_COUNT_reg_n_0_[1] ;
  wire \PREAMBLE_COUNT_reg_n_0_[2] ;
  wire \PREAMBLE_COUNT_reg_n_0_[3] ;
  wire \PREAMBLE_COUNT_reg_n_0_[4] ;
  wire S_TX_ACK_i_1_n_0;
  wire S_TX_ACK_reg_n_0;
  wire \TXD[0]_i_10_n_0 ;
  wire \TXD[0]_i_11_n_0 ;
  wire \TXD[0]_i_1_n_0 ;
  wire \TXD[0]_i_2_n_0 ;
  wire \TXD[0]_i_3_n_0 ;
  wire \TXD[0]_i_6_n_0 ;
  wire \TXD[0]_i_7_n_0 ;
  wire \TXD[0]_i_8_n_0 ;
  wire \TXD[0]_i_9_n_0 ;
  wire \TXD[1]_i_10_n_0 ;
  wire \TXD[1]_i_11_n_0 ;
  wire \TXD[1]_i_12_n_0 ;
  wire \TXD[1]_i_1_n_0 ;
  wire \TXD[1]_i_2_n_0 ;
  wire \TXD[1]_i_3_n_0 ;
  wire \TXD[1]_i_4_n_0 ;
  wire \TXD[1]_i_7_n_0 ;
  wire \TXD[1]_i_8_n_0 ;
  wire \TXD[1]_i_9_n_0 ;
  wire [1:0]TXD_OBUF;
  wire \TXD_reg[0]_i_4_n_0 ;
  wire \TXD_reg[0]_i_5_n_0 ;
  wire \TXD_reg[1]_i_5_n_0 ;
  wire \TXD_reg[1]_i_6_n_0 ;
  wire TXEN_OBUF;
  wire TXEN_i_1_n_0;
  wire \TX_CRC[0]_i_1_n_0 ;
  wire \TX_CRC[0]_i_2_n_0 ;
  wire \TX_CRC[10]_i_3_n_0 ;
  wire \TX_CRC[10]_i_4_n_0 ;
  wire \TX_CRC[10]_i_5_n_0 ;
  wire \TX_CRC[11]_i_1_n_0 ;
  wire \TX_CRC[11]_i_2_n_0 ;
  wire \TX_CRC[11]_i_3_n_0 ;
  wire \TX_CRC[11]_i_4_n_0 ;
  wire \TX_CRC[12]_i_2_n_0 ;
  wire \TX_CRC[12]_i_3_n_0 ;
  wire \TX_CRC[12]_i_4_n_0 ;
  wire \TX_CRC[12]_i_5_n_0 ;
  wire \TX_CRC[12]_i_6_n_0 ;
  wire \TX_CRC[12]_i_7_n_0 ;
  wire \TX_CRC[12]_i_8_n_0 ;
  wire \TX_CRC[13]_i_3_n_0 ;
  wire \TX_CRC[13]_i_4_n_0 ;
  wire \TX_CRC[14]_i_2_n_0 ;
  wire \TX_CRC[14]_i_3_n_0 ;
  wire \TX_CRC[14]_i_4_n_0 ;
  wire \TX_CRC[14]_i_5_n_0 ;
  wire \TX_CRC[15]_i_1_n_0 ;
  wire \TX_CRC[15]_i_2_n_0 ;
  wire \TX_CRC[15]_i_3_n_0 ;
  wire \TX_CRC[15]_i_4_n_0 ;
  wire \TX_CRC[15]_i_5_n_0 ;
  wire \TX_CRC[16]_i_1_n_0 ;
  wire \TX_CRC[16]_i_2_n_0 ;
  wire \TX_CRC[16]_i_3_n_0 ;
  wire \TX_CRC[17]_i_3_n_0 ;
  wire \TX_CRC[17]_i_5_n_0 ;
  wire \TX_CRC[18]_i_2_n_0 ;
  wire \TX_CRC[18]_i_3_n_0 ;
  wire \TX_CRC[18]_i_4_n_0 ;
  wire \TX_CRC[19]_i_1_n_0 ;
  wire \TX_CRC[19]_i_2_n_0 ;
  wire \TX_CRC[1]_i_2_n_0 ;
  wire \TX_CRC[20]_i_1_n_0 ;
  wire \TX_CRC[21]_i_1_n_0 ;
  wire \TX_CRC[22]_i_1_n_0 ;
  wire \TX_CRC[23]_i_1_n_0 ;
  wire \TX_CRC[23]_i_2_n_0 ;
  wire \TX_CRC[23]_i_3_n_0 ;
  wire \TX_CRC[24]_i_3_n_0 ;
  wire \TX_CRC[24]_i_4_n_0 ;
  wire \TX_CRC[25]_i_2_n_0 ;
  wire \TX_CRC[25]_i_3_n_0 ;
  wire \TX_CRC[26]_i_1_n_0 ;
  wire \TX_CRC[26]_i_2_n_0 ;
  wire \TX_CRC[26]_i_3_n_0 ;
  wire \TX_CRC[26]_i_4_n_0 ;
  wire \TX_CRC[27]_i_1_n_0 ;
  wire \TX_CRC[27]_i_2_n_0 ;
  wire \TX_CRC[27]_i_3_n_0 ;
  wire \TX_CRC[27]_i_4_n_0 ;
  wire \TX_CRC[28]_i_1_n_0 ;
  wire \TX_CRC[28]_i_2_n_0 ;
  wire \TX_CRC[28]_i_3_n_0 ;
  wire \TX_CRC[29]_i_2_n_0 ;
  wire \TX_CRC[29]_i_3_n_0 ;
  wire \TX_CRC[29]_i_4_n_0 ;
  wire \TX_CRC[29]_i_5_n_0 ;
  wire \TX_CRC[2]_i_1_n_0 ;
  wire \TX_CRC[2]_i_2_n_0 ;
  wire \TX_CRC[2]_i_3_n_0 ;
  wire \TX_CRC[2]_i_4_n_0 ;
  wire \TX_CRC[30]_i_2_n_0 ;
  wire \TX_CRC[30]_i_3_n_0 ;
  wire \TX_CRC[31]_i_1_n_0 ;
  wire \TX_CRC[31]_i_2_n_0 ;
  wire \TX_CRC[31]_i_3_n_0 ;
  wire \TX_CRC[3]_i_3_n_0 ;
  wire \TX_CRC[3]_i_4_n_0 ;
  wire \TX_CRC[4]_i_2_n_0 ;
  wire \TX_CRC[4]_i_3_n_0 ;
  wire \TX_CRC[4]_i_4_n_0 ;
  wire \TX_CRC[4]_i_5_n_0 ;
  wire \TX_CRC[5]_i_4_n_0 ;
  wire \TX_CRC[5]_i_5_n_0 ;
  wire \TX_CRC[5]_i_6_n_0 ;
  wire \TX_CRC[5]_i_7_n_0 ;
  wire \TX_CRC[5]_i_8_n_0 ;
  wire \TX_CRC[5]_i_9_n_0 ;
  wire \TX_CRC[6]_i_2_n_0 ;
  wire \TX_CRC[6]_i_3_n_0 ;
  wire \TX_CRC[6]_i_4_n_0 ;
  wire \TX_CRC[6]_i_5_n_0 ;
  wire \TX_CRC[6]_i_6_n_0 ;
  wire \TX_CRC[7]_i_1_n_0 ;
  wire \TX_CRC[7]_i_2_n_0 ;
  wire \TX_CRC[7]_i_3_n_0 ;
  wire \TX_CRC[7]_i_4_n_0 ;
  wire \TX_CRC[8]_i_1_n_0 ;
  wire \TX_CRC[9]_i_1_n_0 ;
  wire \TX_CRC[9]_i_2_n_0 ;
  wire \TX_CRC[9]_i_3_n_0 ;
  wire \TX_CRC[9]_i_4_n_0 ;
  wire \TX_CRC_reg[10]_i_1_n_0 ;
  wire \TX_CRC_reg[12]_i_1_n_0 ;
  wire \TX_CRC_reg[13]_i_1_n_0 ;
  wire \TX_CRC_reg[14]_i_1_n_0 ;
  wire \TX_CRC_reg[17]_i_1_n_0 ;
  wire \TX_CRC_reg[18]_i_1_n_0 ;
  wire \TX_CRC_reg[1]_i_1_n_0 ;
  wire \TX_CRC_reg[24]_i_1_n_0 ;
  wire \TX_CRC_reg[25]_i_1_n_0 ;
  wire \TX_CRC_reg[29]_i_1_n_0 ;
  wire \TX_CRC_reg[30]_i_1_n_0 ;
  wire \TX_CRC_reg[3]_i_1_n_0 ;
  wire \TX_CRC_reg[4]_i_1_n_0 ;
  wire \TX_CRC_reg[5]_i_1_n_0 ;
  wire \TX_CRC_reg[6]_i_1_n_0 ;
  wire \TX_CRC_reg_n_0_[0] ;
  wire \TX_CRC_reg_n_0_[10] ;
  wire \TX_CRC_reg_n_0_[11] ;
  wire \TX_CRC_reg_n_0_[12] ;
  wire \TX_CRC_reg_n_0_[13] ;
  wire \TX_CRC_reg_n_0_[14] ;
  wire \TX_CRC_reg_n_0_[15] ;
  wire \TX_CRC_reg_n_0_[16] ;
  wire \TX_CRC_reg_n_0_[17] ;
  wire \TX_CRC_reg_n_0_[18] ;
  wire \TX_CRC_reg_n_0_[19] ;
  wire \TX_CRC_reg_n_0_[20] ;
  wire \TX_CRC_reg_n_0_[21] ;
  wire \TX_CRC_reg_n_0_[22] ;
  wire \TX_CRC_reg_n_0_[23] ;
  wire \TX_CRC_reg_n_0_[8] ;
  wire \TX_CRC_reg_n_0_[9] ;
  wire [10:1]TX_IN_COUNT;
  wire \TX_IN_COUNT[10]_i_1_n_0 ;
  wire \TX_IN_COUNT[10]_i_2_n_0 ;
  wire \TX_IN_COUNT[10]_i_3_n_0 ;
  wire \TX_IN_COUNT[10]_i_4_n_0 ;
  wire \TX_IN_COUNT[1]_i_1_n_0 ;
  wire \TX_IN_COUNT[2]_i_1_n_0 ;
  wire \TX_IN_COUNT[3]_i_1_n_0 ;
  wire \TX_IN_COUNT[4]_i_1_n_0 ;
  wire \TX_IN_COUNT[5]_i_1_n_0 ;
  wire \TX_IN_COUNT[6]_i_1_n_0 ;
  wire \TX_IN_COUNT[7]_i_1_n_0 ;
  wire \TX_IN_COUNT[8]_i_1_n_0 ;
  wire \TX_IN_COUNT[9]_i_1_n_0 ;
  wire TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9;
  wire TX_MEMORY_reg_n_59;
  wire TX_MEMORY_reg_n_67;
  wire [0:0]TX_OUT_COUNT0_in;
  wire \TX_OUT_COUNT[10]_i_1_n_0 ;
  wire \TX_OUT_COUNT[10]_i_2_n_0 ;
  wire \TX_OUT_COUNT[10]_i_3_n_0 ;
  wire \TX_OUT_COUNT[10]_i_4_n_0 ;
  wire \TX_OUT_COUNT[10]_i_5_n_0 ;
  wire \TX_OUT_COUNT[10]_i_6_n_0 ;
  wire \TX_OUT_COUNT[10]_i_7_n_0 ;
  wire \TX_OUT_COUNT[10]_i_8_n_0 ;
  wire \TX_OUT_COUNT[1]_i_1_n_0 ;
  wire \TX_OUT_COUNT[2]_i_1_n_0 ;
  wire \TX_OUT_COUNT[3]_i_1_n_0 ;
  wire \TX_OUT_COUNT[4]_i_1_n_0 ;
  wire \TX_OUT_COUNT[5]_i_1_n_0 ;
  wire \TX_OUT_COUNT[6]_i_1_n_0 ;
  wire \TX_OUT_COUNT[7]_i_1_n_0 ;
  wire \TX_OUT_COUNT[8]_i_1_n_0 ;
  wire \TX_OUT_COUNT[8]_i_2_n_0 ;
  wire \TX_OUT_COUNT[9]_i_1_n_0 ;
  wire \TX_OUT_COUNT_reg_n_0_[0] ;
  wire \TX_OUT_COUNT_reg_n_0_[10] ;
  wire \TX_OUT_COUNT_reg_n_0_[1] ;
  wire \TX_OUT_COUNT_reg_n_0_[2] ;
  wire \TX_OUT_COUNT_reg_n_0_[3] ;
  wire \TX_OUT_COUNT_reg_n_0_[4] ;
  wire \TX_OUT_COUNT_reg_n_0_[5] ;
  wire \TX_OUT_COUNT_reg_n_0_[6] ;
  wire \TX_OUT_COUNT_reg_n_0_[7] ;
  wire \TX_OUT_COUNT_reg_n_0_[8] ;
  wire \TX_OUT_COUNT_reg_n_0_[9] ;
  wire \TX_PACKET_STATE[0]_i_1_n_0 ;
  wire \TX_PACKET_STATE[1]_i_10_n_0 ;
  wire \TX_PACKET_STATE[1]_i_11_n_0 ;
  wire \TX_PACKET_STATE[1]_i_12_n_0 ;
  wire \TX_PACKET_STATE[1]_i_13_n_0 ;
  wire \TX_PACKET_STATE[1]_i_1_n_0 ;
  wire \TX_PACKET_STATE[1]_i_4_n_0 ;
  wire \TX_PACKET_STATE[1]_i_5_n_0 ;
  wire \TX_PACKET_STATE[1]_i_6_n_0 ;
  wire \TX_PACKET_STATE[1]_i_7_n_0 ;
  wire \TX_PACKET_STATE[1]_i_8_n_0 ;
  wire \TX_PACKET_STATE[1]_i_9_n_0 ;
  wire \TX_PACKET_STATE_reg[1]_i_2_n_2 ;
  wire \TX_PACKET_STATE_reg[1]_i_3_n_0 ;
  wire \TX_PACKET_STATE_reg_n_0_[0] ;
  wire \TX_PACKET_STATE_reg_n_0_[1] ;
  wire \TX_PHY_STATE[0]_i_1_n_0 ;
  wire \TX_PHY_STATE[1]_i_1_n_0 ;
  wire \TX_PHY_STATE[2]_i_1_n_0 ;
  wire \TX_PHY_STATE[2]_i_2_n_0 ;
  wire \TX_PHY_STATE[2]_i_3_n_0 ;
  wire \TX_PHY_STATE[2]_i_4_n_0 ;
  wire \TX_PHY_STATE[3]_i_1_n_0 ;
  wire \TX_PHY_STATE[3]_i_2_n_0 ;
  wire \TX_PHY_STATE[3]_i_3_n_0 ;
  wire \TX_PHY_STATE[3]_i_4_n_0 ;
  wire \TX_PHY_STATE[3]_i_5_n_0 ;
  wire \TX_PHY_STATE[4]_i_1_n_0 ;
  wire \TX_PHY_STATE[4]_i_2_n_0 ;
  wire \TX_PHY_STATE[4]_i_3_n_0 ;
  wire \TX_PHY_STATE[4]_i_4_n_0 ;
  wire \TX_PHY_STATE_reg_n_0_[0] ;
  wire \TX_PHY_STATE_reg_n_0_[1] ;
  wire \TX_PHY_STATE_reg_n_0_[2] ;
  wire \TX_PHY_STATE_reg_n_0_[3] ;
  wire \TX_PHY_STATE_reg_n_0_[4] ;
  wire [10:0]TX_READ_ADDRESS;
  wire [10:1]TX_READ_ADDRESS0;
  wire \TX_READ_ADDRESS_rep[0]_i_1_n_0 ;
  wire \TX_READ_ADDRESS_rep[9]_i_1_n_0 ;
  wire \TX_READ_ADDRESS_rep[9]_i_2_n_0 ;
  wire \TX_READ_ADDRESS_rep[9]_i_4_n_0 ;
  wire TX_WRITE;
  wire [10:0]TX_WRITE_ADDRESS;
  wire \TX_WRITE_ADDRESS[0]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[10]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[10]_i_2_n_0 ;
  wire \TX_WRITE_ADDRESS[10]_i_3_n_0 ;
  wire \TX_WRITE_ADDRESS[1]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[2]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[3]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[4]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[5]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[5]_i_2_n_0 ;
  wire \TX_WRITE_ADDRESS[6]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[7]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[8]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[9]_i_1_n_0 ;
  wire \TX_WRITE_ADDRESS[9]_i_2_n_0 ;
  wire [10:0]TX_WRITE_ADDRESS_DEL;
  wire TX_WRITE_i_1_n_0;
  wire p_0_in167_in;
  wire p_0_in66_in;
  wire [1:0]p_16_in;
  wire [1:0]p_17_in;
  wire [1:0]p_18_in;
  wire p_1_in126_in;
  wire p_1_in128_in;
  wire p_1_in130_in;
  wire p_1_in132_in;
  wire p_1_in133_in;
  wire p_1_in135_in;
  wire p_1_in136_in;
  wire p_202_in;
  wire p_206_in;
  wire [1:0]p_20_in;
  wire p_214_in;
  wire p_216_in;
  wire [1:0]p_21_in;
  wire [1:0]p_22_in;
  wire [7:0]slv1_out;
  wire NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED;
  wire NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED;
  wire NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED;
  wire NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED;
  wire NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED;
  wire NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED;
  wire NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED;
  wire NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED;
  wire [31:0]NLW_TX_MEMORY_reg_DOADO_UNCONNECTED;
  wire [31:16]NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED;
  wire [3:0]NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED;
  wire [3:0]NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED;
  wire [7:0]NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED;
  wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED ;
  wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED ;
  wire [2:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED ;
  wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED ;

  FDRE DONE_DEL_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(DONE),
        .Q(DONE_DEL),
        .R(1'b0));
  FDRE DONE_SYNC_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(DONE_DEL),
        .Q(DONE_SYNC),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hBFFFFFFF80000000)) 
    DONE_i_1
       (.I0(GO_SYNC),
        .I1(\TX_PHY_STATE_reg_n_0_[4] ),
        .I2(\TX_PHY_STATE_reg_n_0_[3] ),
        .I3(\TX_PHY_STATE_reg_n_0_[1] ),
        .I4(\TX_PHY_STATE_reg_n_0_[2] ),
        .I5(DONE),
        .O(DONE_i_1_n_0));
  FDRE DONE_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(DONE_i_1_n_0),
        .Q(DONE),
        .R(INTERNAL_RST_reg));
  FDRE GO_DEL_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(GO),
        .Q(GO_DEL),
        .R(1'b0));
  FDRE GO_SYNC_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(GO_DEL),
        .Q(GO_SYNC),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hF704)) 
    GO_i_1
       (.I0(DONE_SYNC),
        .I1(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I2(\TX_PACKET_STATE_reg_n_0_[0] ),
        .I3(GO),
        .O(GO_i_1_n_0));
  FDRE GO_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(GO_i_1_n_0),
        .Q(GO),
        .R(INTERNAL_RST_reg));
  LUT1 #(
    .INIT(2'h1)) 
    \PREAMBLE_COUNT[0]_i_1 
       (.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
        .O(\PREAMBLE_COUNT[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \PREAMBLE_COUNT[1]_i_1 
       (.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
        .I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
        .O(\PREAMBLE_COUNT[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDDD00000020)) 
    \PREAMBLE_COUNT[2]_i_1 
       (.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[4] ),
        .I2(\TX_PHY_STATE_reg_n_0_[0] ),
        .I3(\PREAMBLE_COUNT_reg_n_0_[0] ),
        .I4(\PREAMBLE_COUNT_reg_n_0_[1] ),
        .I5(\PREAMBLE_COUNT_reg_n_0_[2] ),
        .O(\PREAMBLE_COUNT[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \PREAMBLE_COUNT[3]_i_1 
       (.I0(\PREAMBLE_COUNT_reg_n_0_[2] ),
        .I1(\PREAMBLE_COUNT_reg_n_0_[0] ),
        .I2(\PREAMBLE_COUNT_reg_n_0_[1] ),
        .I3(\PREAMBLE_COUNT_reg_n_0_[3] ),
        .O(\PREAMBLE_COUNT[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \PREAMBLE_COUNT[4]_i_1 
       (.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[4] ),
        .I2(\TX_PHY_STATE_reg_n_0_[0] ),
        .O(\PREAMBLE_COUNT[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \PREAMBLE_COUNT[4]_i_2 
       (.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[4] ),
        .O(\PREAMBLE_COUNT[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \PREAMBLE_COUNT[4]_i_3 
       (.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
        .I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
        .I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
        .I3(\PREAMBLE_COUNT_reg_n_0_[2] ),
        .I4(\PREAMBLE_COUNT_reg_n_0_[4] ),
        .O(\PREAMBLE_COUNT[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000001110100)) 
    \PREAMBLE_COUNT[4]_i_4 
       (.I0(\TX_PHY_STATE_reg_n_0_[1] ),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(\TX_PHY_STATE[4]_i_4_n_0 ),
        .I3(\TX_PHY_STATE_reg_n_0_[0] ),
        .I4(GO_SYNC),
        .I5(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\PREAMBLE_COUNT[4]_i_4_n_0 ));
  FDSE \PREAMBLE_COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
        .D(\PREAMBLE_COUNT[0]_i_1_n_0 ),
        .Q(\PREAMBLE_COUNT_reg_n_0_[0] ),
        .S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
  FDSE \PREAMBLE_COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
        .D(\PREAMBLE_COUNT[1]_i_1_n_0 ),
        .Q(\PREAMBLE_COUNT_reg_n_0_[1] ),
        .S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
  FDRE \PREAMBLE_COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\PREAMBLE_COUNT[2]_i_1_n_0 ),
        .Q(\PREAMBLE_COUNT_reg_n_0_[2] ),
        .R(1'b0));
  FDSE \PREAMBLE_COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
        .D(\PREAMBLE_COUNT[3]_i_1_n_0 ),
        .Q(\PREAMBLE_COUNT_reg_n_0_[3] ),
        .S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
  FDSE \PREAMBLE_COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
        .D(\PREAMBLE_COUNT[4]_i_3_n_0 ),
        .Q(\PREAMBLE_COUNT_reg_n_0_[4] ),
        .S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hAE55)) 
    S_TX_ACK_i_1
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(\TX_PACKET_STATE_reg_n_0_[0] ),
        .I2(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
        .I3(S_TX_ACK_reg_n_0),
        .O(S_TX_ACK_i_1_n_0));
  FDRE S_TX_ACK_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(S_TX_ACK_i_1_n_0),
        .Q(S_TX_ACK_reg_n_0),
        .R(INTERNAL_RST_reg));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \TXD[0]_i_1 
       (.I0(\TXD[0]_i_2_n_0 ),
        .I1(\TXD[1]_i_3_n_0 ),
        .I2(TXD_OBUF[0]),
        .O(\TXD[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \TXD[0]_i_10 
       (.I0(p_18_in[0]),
        .I1(TX_MEMORY_reg_n_67),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(p_20_in[0]),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(p_21_in[0]),
        .O(\TXD[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h5F503F3F5F503030)) 
    \TXD[0]_i_11 
       (.I0(slv1_out[5]),
        .I1(slv1_out[7]),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(p_16_in[0]),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(p_17_in[0]),
        .O(\TXD[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \TXD[0]_i_2 
       (.I0(\TXD[0]_i_3_n_0 ),
        .I1(\TXD_reg[0]_i_4_n_0 ),
        .I2(\TX_PHY_STATE_reg_n_0_[4] ),
        .I3(\TXD_reg[0]_i_5_n_0 ),
        .I4(\TX_PHY_STATE_reg_n_0_[3] ),
        .I5(\TXD[0]_i_6_n_0 ),
        .O(\TXD[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h47FF4700)) 
    \TXD[0]_i_3 
       (.I0(p_1_in126_in),
        .I1(\TX_PHY_STATE_reg_n_0_[0] ),
        .I2(p_1_in130_in),
        .I3(\TX_PHY_STATE_reg_n_0_[2] ),
        .I4(\TXD[0]_i_7_n_0 ),
        .O(\TXD[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hDFD5FFFF)) 
    \TXD[0]_i_6 
       (.I0(\TX_PHY_STATE_reg_n_0_[1] ),
        .I1(p_22_in[0]),
        .I2(\TX_PHY_STATE_reg_n_0_[0] ),
        .I3(TX_MEMORY_reg_n_59),
        .I4(\TX_PHY_STATE_reg_n_0_[2] ),
        .O(\TXD[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \TXD[0]_i_7 
       (.I0(p_1_in133_in),
        .I1(p_1_in136_in),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(\TX_CRC_reg_n_0_[9] ),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(\TX_CRC_reg_n_0_[11] ),
        .O(\TXD[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \TXD[0]_i_8 
       (.I0(\TX_CRC_reg_n_0_[21] ),
        .I1(\TX_CRC_reg_n_0_[23] ),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(slv1_out[1]),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(slv1_out[3]),
        .O(\TXD[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \TXD[0]_i_9 
       (.I0(\TX_CRC_reg_n_0_[13] ),
        .I1(\TX_CRC_reg_n_0_[15] ),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(\TX_CRC_reg_n_0_[17] ),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(\TX_CRC_reg_n_0_[19] ),
        .O(\TXD[0]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \TXD[1]_i_1 
       (.I0(\TXD[1]_i_2_n_0 ),
        .I1(\TXD[1]_i_3_n_0 ),
        .I2(TXD_OBUF[1]),
        .O(\TXD[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \TXD[1]_i_10 
       (.I0(\TX_CRC_reg_n_0_[12] ),
        .I1(\TX_CRC_reg_n_0_[14] ),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(\TX_CRC_reg_n_0_[16] ),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(\TX_CRC_reg_n_0_[18] ),
        .O(\TXD[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \TXD[1]_i_11 
       (.I0(p_18_in[1]),
        .I1(p_0_in66_in),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(p_20_in[1]),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(p_21_in[1]),
        .O(\TXD[1]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h5F503F3F5F503030)) 
    \TXD[1]_i_12 
       (.I0(slv1_out[4]),
        .I1(slv1_out[6]),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(p_16_in[1]),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(p_17_in[1]),
        .O(\TXD[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \TXD[1]_i_2 
       (.I0(\TXD[1]_i_4_n_0 ),
        .I1(\TXD_reg[1]_i_5_n_0 ),
        .I2(\TX_PHY_STATE_reg_n_0_[4] ),
        .I3(\TXD_reg[1]_i_6_n_0 ),
        .I4(\TX_PHY_STATE_reg_n_0_[3] ),
        .I5(\TXD[1]_i_7_n_0 ),
        .O(\TXD[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hBFFFFFFE)) 
    \TXD[1]_i_3 
       (.I0(\TX_PHY_STATE_reg_n_0_[0] ),
        .I1(\TX_PHY_STATE_reg_n_0_[3] ),
        .I2(\TX_PHY_STATE_reg_n_0_[4] ),
        .I3(\TX_PHY_STATE_reg_n_0_[1] ),
        .I4(\TX_PHY_STATE_reg_n_0_[2] ),
        .O(\TXD[1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h47FF4700)) 
    \TXD[1]_i_4 
       (.I0(\TX_CRC_reg_n_0_[0] ),
        .I1(\TX_PHY_STATE_reg_n_0_[0] ),
        .I2(p_1_in128_in),
        .I3(\TX_PHY_STATE_reg_n_0_[2] ),
        .I4(\TXD[1]_i_8_n_0 ),
        .O(\TXD[1]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hA8882808)) 
    \TXD[1]_i_7 
       (.I0(\TX_PHY_STATE_reg_n_0_[2] ),
        .I1(\TX_PHY_STATE_reg_n_0_[0] ),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(p_0_in167_in),
        .I4(p_22_in[1]),
        .O(\TXD[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \TXD[1]_i_8 
       (.I0(p_1_in132_in),
        .I1(p_1_in135_in),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(\TX_CRC_reg_n_0_[8] ),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(\TX_CRC_reg_n_0_[10] ),
        .O(\TXD[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \TXD[1]_i_9 
       (.I0(\TX_CRC_reg_n_0_[20] ),
        .I1(\TX_CRC_reg_n_0_[22] ),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(slv1_out[0]),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(slv1_out[2]),
        .O(\TXD[1]_i_9_n_0 ));
  FDRE \TXD_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\TXD[0]_i_1_n_0 ),
        .Q(TXD_OBUF[0]),
        .R(INTERNAL_RST_reg));
  MUXF7 \TXD_reg[0]_i_4 
       (.I0(\TXD[0]_i_8_n_0 ),
        .I1(\TXD[0]_i_9_n_0 ),
        .O(\TXD_reg[0]_i_4_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  MUXF7 \TXD_reg[0]_i_5 
       (.I0(\TXD[0]_i_10_n_0 ),
        .I1(\TXD[0]_i_11_n_0 ),
        .O(\TXD_reg[0]_i_5_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDRE \TXD_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\TXD[1]_i_1_n_0 ),
        .Q(TXD_OBUF[1]),
        .R(INTERNAL_RST_reg));
  MUXF7 \TXD_reg[1]_i_5 
       (.I0(\TXD[1]_i_9_n_0 ),
        .I1(\TXD[1]_i_10_n_0 ),
        .O(\TXD_reg[1]_i_5_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  MUXF7 \TXD_reg[1]_i_6 
       (.I0(\TXD[1]_i_11_n_0 ),
        .I1(\TXD[1]_i_12_n_0 ),
        .O(\TXD_reg[1]_i_6_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  LUT6 #(
    .INIT(64'h7F7FFFFF00000100)) 
    TXEN_i_1
       (.I0(\TX_PHY_STATE_reg_n_0_[4] ),
        .I1(\TX_PHY_STATE_reg_n_0_[3] ),
        .I2(\TX_PHY_STATE_reg_n_0_[2] ),
        .I3(\TX_PHY_STATE_reg_n_0_[0] ),
        .I4(\TX_PHY_STATE_reg_n_0_[1] ),
        .I5(TXEN_OBUF),
        .O(TXEN_i_1_n_0));
  FDRE TXEN_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TXEN_i_1_n_0),
        .Q(TXEN_OBUF),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'h8BB8744774478BB8)) 
    \TX_CRC[0]_i_1 
       (.I0(\TX_CRC[0]_i_2_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(p_0_in167_in),
        .I3(p_20_in[1]),
        .I4(slv1_out[6]),
        .I5(slv1_out[0]),
        .O(\TX_CRC[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[0]_i_2 
       (.I0(p_16_in[1]),
        .I1(p_0_in66_in),
        .O(\TX_CRC[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[10]_i_2 
       (.I0(p_21_in[1]),
        .I1(p_20_in[1]),
        .I2(\TX_CRC[10]_i_4_n_0 ),
        .I3(p_21_in[0]),
        .I4(p_22_in[0]),
        .O(NEXTCRC32_D80189_out));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[10]_i_3 
       (.I0(slv1_out[2]),
        .I1(slv1_out[3]),
        .I2(p_18_in[0]),
        .I3(slv1_out[0]),
        .I4(\TX_CRC[10]_i_5_n_0 ),
        .O(\TX_CRC[10]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[10]_i_4 
       (.I0(p_1_in128_in),
        .I1(slv1_out[5]),
        .I2(slv1_out[0]),
        .I3(slv1_out[3]),
        .I4(slv1_out[2]),
        .O(\TX_CRC[10]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[10]_i_5 
       (.I0(slv1_out[5]),
        .I1(p_1_in128_in),
        .I2(p_16_in[1]),
        .I3(p_17_in[1]),
        .I4(p_17_in[0]),
        .O(\TX_CRC[10]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hF0660F990F99F066)) 
    \TX_CRC[11]_i_1 
       (.I0(p_22_in[1]),
        .I1(\TX_CRC[11]_i_2_n_0 ),
        .I2(\TX_CRC[11]_i_3_n_0 ),
        .I3(\TX_PHY_STATE_reg_n_0_[2] ),
        .I4(p_1_in130_in),
        .I5(slv1_out[4]),
        .O(\TX_CRC[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[11]_i_2 
       (.I0(p_20_in[0]),
        .I1(p_20_in[1]),
        .I2(slv1_out[1]),
        .I3(slv1_out[0]),
        .I4(slv1_out[3]),
        .I5(p_21_in[0]),
        .O(\TX_CRC[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[11]_i_3 
       (.I0(p_16_in[1]),
        .I1(p_17_in[0]),
        .I2(slv1_out[0]),
        .I3(p_16_in[0]),
        .I4(slv1_out[1]),
        .I5(\TX_CRC[11]_i_4_n_0 ),
        .O(\TX_CRC[11]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[11]_i_4 
       (.I0(slv1_out[3]),
        .I1(p_18_in[1]),
        .O(\TX_CRC[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[12]_i_2 
       (.I0(slv1_out[0]),
        .I1(\TX_CRC[12]_i_4_n_0 ),
        .I2(slv1_out[4]),
        .I3(slv1_out[1]),
        .I4(p_22_in[1]),
        .I5(\TX_CRC[12]_i_5_n_0 ),
        .O(\TX_CRC[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[12]_i_3 
       (.I0(p_18_in[0]),
        .I1(p_16_in[0]),
        .I2(p_16_in[1]),
        .I3(p_0_in66_in),
        .I4(\TX_CRC[12]_i_6_n_0 ),
        .O(\TX_CRC[12]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[12]_i_4 
       (.I0(slv1_out[6]),
        .I1(slv1_out[2]),
        .O(\TX_CRC[12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[12]_i_5 
       (.I0(\TX_CRC[18]_i_4_n_0 ),
        .I1(p_22_in[0]),
        .I2(p_20_in[0]),
        .I3(slv1_out[5]),
        .I4(p_1_in132_in),
        .I5(p_20_in[1]),
        .O(\TX_CRC[12]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[12]_i_6 
       (.I0(p_17_in[1]),
        .I1(p_1_in132_in),
        .I2(slv1_out[5]),
        .I3(p_18_in[1]),
        .I4(\TX_CRC[12]_i_7_n_0 ),
        .I5(\TX_CRC[12]_i_8_n_0 ),
        .O(\TX_CRC[12]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[12]_i_7 
       (.I0(slv1_out[4]),
        .I1(slv1_out[1]),
        .O(\TX_CRC[12]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \TX_CRC[12]_i_8 
       (.I0(slv1_out[0]),
        .I1(slv1_out[2]),
        .I2(slv1_out[6]),
        .O(\TX_CRC[12]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[13]_i_2 
       (.I0(p_22_in[0]),
        .I1(p_21_in[0]),
        .I2(TX_MEMORY_reg_n_59),
        .I3(\TX_CRC[13]_i_4_n_0 ),
        .I4(\TX_CRC[18]_i_4_n_0 ),
        .I5(p_20_in[0]),
        .O(NEXTCRC32_D80195_out));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[13]_i_3 
       (.I0(p_17_in[1]),
        .I1(p_17_in[0]),
        .I2(TX_MEMORY_reg_n_67),
        .I3(\TX_CRC[13]_i_4_n_0 ),
        .I4(p_18_in[0]),
        .I5(\TX_CRC[17]_i_5_n_0 ),
        .O(\TX_CRC[13]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[13]_i_4 
       (.I0(p_1_in133_in),
        .I1(slv1_out[6]),
        .I2(slv1_out[1]),
        .I3(slv1_out[5]),
        .I4(\TX_CRC[3]_i_4_n_0 ),
        .O(\TX_CRC[13]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[14]_i_2 
       (.I0(p_21_in[1]),
        .I1(p_0_in167_in),
        .I2(p_21_in[0]),
        .I3(\TX_CRC[14]_i_4_n_0 ),
        .I4(TX_MEMORY_reg_n_59),
        .I5(p_22_in[1]),
        .O(\TX_CRC[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[14]_i_3 
       (.I0(p_18_in[1]),
        .I1(slv1_out[3]),
        .I2(p_17_in[1]),
        .I3(\TX_CRC[14]_i_5_n_0 ),
        .I4(TX_MEMORY_reg_n_67),
        .I5(p_0_in66_in),
        .O(\TX_CRC[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[14]_i_4 
       (.I0(p_1_in135_in),
        .I1(slv1_out[7]),
        .I2(slv1_out[4]),
        .I3(slv1_out[3]),
        .I4(slv1_out[6]),
        .I5(slv1_out[2]),
        .O(\TX_CRC[14]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[14]_i_5 
       (.I0(p_17_in[0]),
        .I1(slv1_out[2]),
        .I2(slv1_out[6]),
        .I3(slv1_out[4]),
        .I4(slv1_out[7]),
        .I5(p_1_in135_in),
        .O(\TX_CRC[14]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h9F90606F909F6F60)) 
    \TX_CRC[15]_i_1 
       (.I0(\TX_CRC[15]_i_2_n_0 ),
        .I1(\TX_CRC[15]_i_3_n_0 ),
        .I2(\TX_PHY_STATE_reg_n_0_[2] ),
        .I3(\TX_CRC[15]_i_4_n_0 ),
        .I4(slv1_out[3]),
        .I5(\TX_CRC[15]_i_5_n_0 ),
        .O(\TX_CRC[15]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[15]_i_2 
       (.I0(p_18_in[1]),
        .I1(slv1_out[4]),
        .O(\TX_CRC[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[15]_i_3 
       (.I0(TX_MEMORY_reg_n_67),
        .I1(p_17_in[0]),
        .I2(slv1_out[5]),
        .I3(p_18_in[0]),
        .I4(slv1_out[7]),
        .I5(p_1_in136_in),
        .O(\TX_CRC[15]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[15]_i_4 
       (.I0(slv1_out[4]),
        .I1(p_22_in[1]),
        .O(\TX_CRC[15]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[15]_i_5 
       (.I0(p_21_in[0]),
        .I1(p_22_in[0]),
        .I2(slv1_out[5]),
        .I3(TX_MEMORY_reg_n_59),
        .I4(slv1_out[7]),
        .I5(p_1_in136_in),
        .O(\TX_CRC[15]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h9F90606F909F6F60)) 
    \TX_CRC[16]_i_1 
       (.I0(p_18_in[1]),
        .I1(\TX_CRC[16]_i_2_n_0 ),
        .I2(\TX_PHY_STATE_reg_n_0_[2] ),
        .I3(slv1_out[4]),
        .I4(slv1_out[0]),
        .I5(\TX_CRC[16]_i_3_n_0 ),
        .O(\TX_CRC[16]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[16]_i_2 
       (.I0(p_18_in[0]),
        .I1(slv1_out[4]),
        .I2(slv1_out[5]),
        .I3(\TX_CRC_reg_n_0_[8] ),
        .I4(p_16_in[1]),
        .O(\TX_CRC[16]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[16]_i_3 
       (.I0(p_20_in[1]),
        .I1(p_22_in[1]),
        .I2(p_22_in[0]),
        .I3(slv1_out[5]),
        .I4(\TX_CRC_reg_n_0_[8] ),
        .O(\TX_CRC[16]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[17]_i_2 
       (.I0(slv1_out[5]),
        .I1(p_202_in),
        .I2(p_20_in[0]),
        .I3(slv1_out[1]),
        .I4(p_22_in[0]),
        .I5(p_0_in167_in),
        .O(NEXTCRC32_D80203_out));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[17]_i_3 
       (.I0(slv1_out[5]),
        .I1(\TX_CRC[17]_i_5_n_0 ),
        .I2(\TX_CRC_reg_n_0_[9] ),
        .I3(slv1_out[6]),
        .I4(slv1_out[1]),
        .I5(p_18_in[0]),
        .O(\TX_CRC[17]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[17]_i_4 
       (.I0(slv1_out[6]),
        .I1(\TX_CRC_reg_n_0_[9] ),
        .O(p_202_in));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[17]_i_5 
       (.I0(p_0_in66_in),
        .I1(p_16_in[0]),
        .O(\TX_CRC[17]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[18]_i_2 
       (.I0(slv1_out[6]),
        .I1(TX_MEMORY_reg_n_59),
        .I2(\TX_CRC_reg_n_0_[10] ),
        .I3(slv1_out[7]),
        .I4(slv1_out[2]),
        .I5(\TX_CRC[18]_i_4_n_0 ),
        .O(\TX_CRC[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[18]_i_3 
       (.I0(slv1_out[6]),
        .I1(\TX_CRC[29]_i_5_n_0 ),
        .I2(\TX_CRC_reg_n_0_[10] ),
        .I3(slv1_out[7]),
        .I4(slv1_out[2]),
        .I5(p_17_in[1]),
        .O(\TX_CRC[18]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[18]_i_4 
       (.I0(p_0_in167_in),
        .I1(p_21_in[1]),
        .O(\TX_CRC[18]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h8778B44BB44B8778)) 
    \TX_CRC[19]_i_1 
       (.I0(\TX_CRC[19]_i_2_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(slv1_out[3]),
        .I3(p_206_in),
        .I4(TX_MEMORY_reg_n_59),
        .I5(p_21_in[0]),
        .O(\TX_CRC[19]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[19]_i_2 
       (.I0(TX_MEMORY_reg_n_67),
        .I1(p_17_in[0]),
        .O(\TX_CRC[19]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[19]_i_3 
       (.I0(slv1_out[7]),
        .I1(\TX_CRC_reg_n_0_[11] ),
        .O(p_206_in));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[1]_i_2 
       (.I0(\TX_CRC[23]_i_3_n_0 ),
        .I1(slv1_out[1]),
        .I2(slv1_out[7]),
        .I3(TX_MEMORY_reg_n_59),
        .I4(slv1_out[0]),
        .I5(slv1_out[6]),
        .O(\TX_CRC[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[1]_i_3 
       (.I0(\TX_CRC[23]_i_2_n_0 ),
        .I1(slv1_out[0]),
        .I2(TX_MEMORY_reg_n_67),
        .I3(slv1_out[7]),
        .I4(slv1_out[1]),
        .O(NEXTCRC32_D8070_out));
  LUT5 #(
    .INIT(32'hB84747B8)) 
    \TX_CRC[20]_i_1 
       (.I0(p_18_in[1]),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(p_22_in[1]),
        .I3(slv1_out[4]),
        .I4(\TX_CRC_reg_n_0_[12] ),
        .O(\TX_CRC[20]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB84747B8)) 
    \TX_CRC[21]_i_1 
       (.I0(p_18_in[0]),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(p_22_in[0]),
        .I3(\TX_CRC_reg_n_0_[13] ),
        .I4(slv1_out[5]),
        .O(\TX_CRC[21]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB84747B8)) 
    \TX_CRC[22]_i_1 
       (.I0(p_16_in[1]),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(p_20_in[1]),
        .I3(\TX_CRC_reg_n_0_[14] ),
        .I4(slv1_out[0]),
        .O(\TX_CRC[22]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h87B4784BB4874B78)) 
    \TX_CRC[23]_i_1 
       (.I0(\TX_CRC[23]_i_2_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(slv1_out[0]),
        .I3(\TX_CRC[23]_i_3_n_0 ),
        .I4(p_214_in),
        .I5(slv1_out[6]),
        .O(\TX_CRC[23]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \TX_CRC[23]_i_2 
       (.I0(p_0_in66_in),
        .I1(p_16_in[1]),
        .I2(p_16_in[0]),
        .I3(slv1_out[6]),
        .O(\TX_CRC[23]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \TX_CRC[23]_i_3 
       (.I0(p_20_in[1]),
        .I1(p_20_in[0]),
        .I2(p_0_in167_in),
        .O(\TX_CRC[23]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[23]_i_4 
       (.I0(slv1_out[1]),
        .I1(\TX_CRC_reg_n_0_[15] ),
        .O(p_214_in));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[24]_i_2 
       (.I0(\TX_CRC[24]_i_4_n_0 ),
        .I1(TX_MEMORY_reg_n_59),
        .I2(slv1_out[2]),
        .I3(\TX_CRC_reg_n_0_[16] ),
        .I4(p_20_in[0]),
        .I5(p_21_in[1]),
        .O(NEXTCRC32_D80217_out));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[24]_i_3 
       (.I0(slv1_out[7]),
        .I1(p_16_in[0]),
        .I2(TX_MEMORY_reg_n_67),
        .I3(p_216_in),
        .I4(slv1_out[1]),
        .I5(p_17_in[1]),
        .O(\TX_CRC[24]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[24]_i_4 
       (.I0(slv1_out[7]),
        .I1(slv1_out[1]),
        .O(\TX_CRC[24]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[24]_i_5 
       (.I0(\TX_CRC_reg_n_0_[16] ),
        .I1(slv1_out[2]),
        .O(p_216_in));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[25]_i_2 
       (.I0(slv1_out[3]),
        .I1(\TX_CRC_reg_n_0_[17] ),
        .I2(slv1_out[2]),
        .I3(p_21_in[1]),
        .I4(p_21_in[0]),
        .O(\TX_CRC[25]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[25]_i_3 
       (.I0(slv1_out[2]),
        .I1(p_17_in[1]),
        .I2(slv1_out[3]),
        .I3(\TX_CRC_reg_n_0_[17] ),
        .I4(p_17_in[0]),
        .O(\TX_CRC[25]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996FFFF69960000)) 
    \TX_CRC[26]_i_1 
       (.I0(p_16_in[1]),
        .I1(\TX_CRC[26]_i_2_n_0 ),
        .I2(p_0_in66_in),
        .I3(p_17_in[0]),
        .I4(\TX_PHY_STATE_reg_n_0_[2] ),
        .I5(\TX_CRC[26]_i_3_n_0 ),
        .O(\TX_CRC[26]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[26]_i_2 
       (.I0(p_18_in[1]),
        .I1(slv1_out[6]),
        .I2(slv1_out[3]),
        .I3(slv1_out[0]),
        .I4(\TX_CRC_reg_n_0_[18] ),
        .I5(slv1_out[4]),
        .O(\TX_CRC[26]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \TX_CRC[26]_i_3 
       (.I0(p_0_in167_in),
        .I1(p_20_in[1]),
        .I2(\TX_CRC[26]_i_4_n_0 ),
        .I3(p_22_in[1]),
        .O(\TX_CRC[26]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[26]_i_4 
       (.I0(p_21_in[0]),
        .I1(slv1_out[6]),
        .I2(slv1_out[3]),
        .I3(slv1_out[0]),
        .I4(\TX_CRC_reg_n_0_[18] ),
        .I5(slv1_out[4]),
        .O(\TX_CRC[26]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6F90906F609F9F60)) 
    \TX_CRC[27]_i_1 
       (.I0(p_18_in[1]),
        .I1(\TX_CRC[27]_i_2_n_0 ),
        .I2(\TX_PHY_STATE_reg_n_0_[2] ),
        .I3(slv1_out[4]),
        .I4(slv1_out[7]),
        .I5(\TX_CRC[27]_i_3_n_0 ),
        .O(\TX_CRC[27]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[27]_i_2 
       (.I0(p_18_in[0]),
        .I1(p_16_in[0]),
        .I2(slv1_out[1]),
        .I3(slv1_out[5]),
        .I4(\TX_CRC_reg_n_0_[19] ),
        .I5(TX_MEMORY_reg_n_67),
        .O(\TX_CRC[27]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[27]_i_3 
       (.I0(\TX_CRC[27]_i_4_n_0 ),
        .I1(p_22_in[1]),
        .I2(slv1_out[1]),
        .I3(TX_MEMORY_reg_n_59),
        .I4(slv1_out[5]),
        .I5(\TX_CRC_reg_n_0_[19] ),
        .O(\TX_CRC[27]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[27]_i_4 
       (.I0(p_22_in[0]),
        .I1(p_20_in[0]),
        .O(\TX_CRC[27]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h906F9F60)) 
    \TX_CRC[28]_i_1 
       (.I0(slv1_out[2]),
        .I1(\TX_CRC[28]_i_2_n_0 ),
        .I2(\TX_PHY_STATE_reg_n_0_[2] ),
        .I3(slv1_out[5]),
        .I4(\TX_CRC[28]_i_3_n_0 ),
        .O(\TX_CRC[28]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[28]_i_2 
       (.I0(slv1_out[6]),
        .I1(\TX_CRC_reg_n_0_[20] ),
        .I2(p_0_in66_in),
        .I3(p_17_in[1]),
        .I4(p_18_in[0]),
        .O(\TX_CRC[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[28]_i_3 
       (.I0(p_0_in167_in),
        .I1(p_22_in[0]),
        .I2(slv1_out[2]),
        .I3(p_21_in[1]),
        .I4(slv1_out[6]),
        .I5(\TX_CRC_reg_n_0_[20] ),
        .O(\TX_CRC[28]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[29]_i_2 
       (.I0(\TX_CRC[29]_i_4_n_0 ),
        .I1(p_0_in167_in),
        .I2(p_21_in[0]),
        .I3(\TX_CRC_reg_n_0_[21] ),
        .I4(slv1_out[7]),
        .I5(TX_MEMORY_reg_n_59),
        .O(\TX_CRC[29]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[29]_i_3 
       (.I0(slv1_out[3]),
        .I1(p_17_in[0]),
        .I2(\TX_CRC_reg_n_0_[21] ),
        .I3(slv1_out[7]),
        .I4(slv1_out[6]),
        .I5(\TX_CRC[29]_i_5_n_0 ),
        .O(\TX_CRC[29]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[29]_i_4 
       (.I0(slv1_out[3]),
        .I1(slv1_out[6]),
        .O(\TX_CRC[29]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[29]_i_5 
       (.I0(TX_MEMORY_reg_n_67),
        .I1(p_0_in66_in),
        .O(\TX_CRC[29]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB4874B78)) 
    \TX_CRC[2]_i_1 
       (.I0(\TX_CRC[2]_i_2_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(slv1_out[0]),
        .I3(\TX_CRC[2]_i_3_n_0 ),
        .I4(\TX_CRC[2]_i_4_n_0 ),
        .O(\TX_CRC[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[2]_i_2 
       (.I0(TX_MEMORY_reg_n_67),
        .I1(p_0_in66_in),
        .I2(p_16_in[0]),
        .I3(p_17_in[1]),
        .I4(p_16_in[1]),
        .O(\TX_CRC[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[2]_i_3 
       (.I0(p_20_in[0]),
        .I1(p_0_in167_in),
        .I2(p_21_in[1]),
        .I3(p_20_in[1]),
        .I4(TX_MEMORY_reg_n_59),
        .O(\TX_CRC[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \TX_CRC[2]_i_4 
       (.I0(slv1_out[6]),
        .I1(slv1_out[7]),
        .I2(slv1_out[1]),
        .I3(slv1_out[2]),
        .O(\TX_CRC[2]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[30]_i_2 
       (.I0(p_22_in[1]),
        .I1(slv1_out[4]),
        .I2(TX_MEMORY_reg_n_59),
        .I3(slv1_out[7]),
        .I4(\TX_CRC_reg_n_0_[22] ),
        .O(\TX_CRC[30]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[30]_i_3 
       (.I0(slv1_out[4]),
        .I1(p_18_in[1]),
        .I2(slv1_out[7]),
        .I3(\TX_CRC_reg_n_0_[22] ),
        .I4(TX_MEMORY_reg_n_67),
        .O(\TX_CRC[30]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00000008)) 
    \TX_CRC[31]_i_1 
       (.I0(\TX_PHY_STATE_reg_n_0_[2] ),
        .I1(\TX_PHY_STATE_reg_n_0_[0] ),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(\TX_PHY_STATE_reg_n_0_[4] ),
        .I4(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_CRC[31]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h10101000)) 
    \TX_CRC[31]_i_2 
       (.I0(\TX_PHY_STATE_reg_n_0_[4] ),
        .I1(\TX_PHY_STATE_reg_n_0_[1] ),
        .I2(\TX_PHY_STATE_reg_n_0_[0] ),
        .I3(\TX_PHY_STATE_reg_n_0_[2] ),
        .I4(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_CRC[31]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB84747B8)) 
    \TX_CRC[31]_i_3 
       (.I0(p_18_in[0]),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(p_22_in[0]),
        .I3(\TX_CRC_reg_n_0_[23] ),
        .I4(slv1_out[5]),
        .O(\TX_CRC[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[3]_i_2 
       (.I0(\TX_CRC[3]_i_4_n_0 ),
        .I1(p_21_in[1]),
        .I2(p_21_in[0]),
        .I3(TX_MEMORY_reg_n_59),
        .I4(slv1_out[1]),
        .I5(p_20_in[0]),
        .O(NEXTCRC32_D80177_out));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[3]_i_3 
       (.I0(\TX_CRC[3]_i_4_n_0 ),
        .I1(p_16_in[0]),
        .I2(TX_MEMORY_reg_n_67),
        .I3(p_17_in[0]),
        .I4(slv1_out[1]),
        .I5(p_17_in[1]),
        .O(\TX_CRC[3]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \TX_CRC[3]_i_4 
       (.I0(slv1_out[7]),
        .I1(slv1_out[2]),
        .I2(slv1_out[3]),
        .O(\TX_CRC[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[4]_i_2 
       (.I0(p_21_in[1]),
        .I1(p_0_in167_in),
        .I2(\TX_CRC[4]_i_4_n_0 ),
        .I3(p_22_in[1]),
        .I4(p_21_in[0]),
        .O(\TX_CRC[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[4]_i_3 
       (.I0(slv1_out[4]),
        .I1(slv1_out[3]),
        .I2(slv1_out[0]),
        .I3(p_18_in[1]),
        .I4(\TX_CRC[4]_i_5_n_0 ),
        .O(\TX_CRC[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[4]_i_4 
       (.I0(p_20_in[1]),
        .I1(slv1_out[2]),
        .I2(slv1_out[6]),
        .I3(slv1_out[3]),
        .I4(slv1_out[0]),
        .I5(slv1_out[4]),
        .O(\TX_CRC[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[4]_i_5 
       (.I0(p_17_in[1]),
        .I1(slv1_out[6]),
        .I2(slv1_out[2]),
        .I3(p_17_in[0]),
        .I4(p_16_in[1]),
        .I5(p_0_in66_in),
        .O(\TX_CRC[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[5]_i_2 
       (.I0(\TX_CRC[5]_i_4_n_0 ),
        .I1(p_20_in[1]),
        .I2(p_0_in167_in),
        .I3(TX_MEMORY_reg_n_59),
        .I4(\TX_CRC[5]_i_5_n_0 ),
        .I5(\TX_CRC[5]_i_6_n_0 ),
        .O(NEXTCRC32_D80181_out));
  LUT5 #(
    .INIT(32'h96696996)) 
    \TX_CRC[5]_i_3 
       (.I0(TX_MEMORY_reg_n_67),
        .I1(p_17_in[0]),
        .I2(p_16_in[1]),
        .I3(p_0_in66_in),
        .I4(\TX_CRC[5]_i_7_n_0 ),
        .O(NEXTCRC32_D8074_out));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[5]_i_4 
       (.I0(p_21_in[0]),
        .I1(p_22_in[0]),
        .O(\TX_CRC[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[5]_i_5 
       (.I0(p_20_in[0]),
        .I1(\TX_CRC[6]_i_6_n_0 ),
        .I2(slv1_out[0]),
        .I3(slv1_out[5]),
        .I4(slv1_out[6]),
        .I5(slv1_out[3]),
        .O(\TX_CRC[5]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[5]_i_6 
       (.I0(p_22_in[1]),
        .I1(slv1_out[1]),
        .O(\TX_CRC[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[5]_i_7 
       (.I0(\TX_CRC[5]_i_8_n_0 ),
        .I1(slv1_out[1]),
        .I2(slv1_out[4]),
        .I3(slv1_out[7]),
        .I4(\TX_CRC[5]_i_9_n_0 ),
        .I5(p_18_in[1]),
        .O(\TX_CRC[5]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[5]_i_8 
       (.I0(p_18_in[0]),
        .I1(p_16_in[0]),
        .O(\TX_CRC[5]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \TX_CRC[5]_i_9 
       (.I0(slv1_out[0]),
        .I1(slv1_out[5]),
        .I2(slv1_out[6]),
        .I3(slv1_out[3]),
        .O(\TX_CRC[5]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[6]_i_2 
       (.I0(\TX_CRC[18]_i_4_n_0 ),
        .I1(p_22_in[1]),
        .I2(slv1_out[1]),
        .I3(\TX_CRC[6]_i_4_n_0 ),
        .I4(p_22_in[0]),
        .I5(p_20_in[0]),
        .O(\TX_CRC[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[6]_i_3 
       (.I0(p_18_in[0]),
        .I1(p_16_in[0]),
        .I2(slv1_out[2]),
        .I3(slv1_out[6]),
        .I4(p_17_in[1]),
        .I5(\TX_CRC[6]_i_5_n_0 ),
        .O(\TX_CRC[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[6]_i_4 
       (.I0(TX_MEMORY_reg_n_59),
        .I1(slv1_out[2]),
        .I2(slv1_out[6]),
        .I3(slv1_out[5]),
        .I4(slv1_out[7]),
        .I5(slv1_out[4]),
        .O(\TX_CRC[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[6]_i_5 
       (.I0(p_0_in66_in),
        .I1(TX_MEMORY_reg_n_67),
        .I2(\TX_CRC[6]_i_6_n_0 ),
        .I3(slv1_out[5]),
        .I4(slv1_out[1]),
        .I5(p_18_in[1]),
        .O(\TX_CRC[6]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CRC[6]_i_6 
       (.I0(slv1_out[7]),
        .I1(slv1_out[4]),
        .O(\TX_CRC[6]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h690096FF69FF9600)) 
    \TX_CRC[7]_i_1 
       (.I0(slv1_out[5]),
        .I1(p_18_in[0]),
        .I2(\TX_CRC[7]_i_2_n_0 ),
        .I3(\TX_PHY_STATE_reg_n_0_[2] ),
        .I4(\TX_CRC[7]_i_3_n_0 ),
        .I5(\TX_CRC[7]_i_4_n_0 ),
        .O(\TX_CRC[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \TX_CRC[7]_i_2 
       (.I0(TX_MEMORY_reg_n_67),
        .I1(p_16_in[1]),
        .I2(p_17_in[1]),
        .I3(p_17_in[0]),
        .O(\TX_CRC[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \TX_CRC[7]_i_3 
       (.I0(slv1_out[3]),
        .I1(slv1_out[2]),
        .I2(slv1_out[7]),
        .I3(slv1_out[0]),
        .O(\TX_CRC[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[7]_i_4 
       (.I0(p_20_in[1]),
        .I1(p_21_in[1]),
        .I2(slv1_out[5]),
        .I3(TX_MEMORY_reg_n_59),
        .I4(p_21_in[0]),
        .I5(p_22_in[0]),
        .O(\TX_CRC[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hF0660F990F99F066)) 
    \TX_CRC[8]_i_1 
       (.I0(p_22_in[1]),
        .I1(\TX_CRC[11]_i_2_n_0 ),
        .I2(\TX_CRC[11]_i_3_n_0 ),
        .I3(\TX_PHY_STATE_reg_n_0_[2] ),
        .I4(\TX_CRC_reg_n_0_[0] ),
        .I5(slv1_out[4]),
        .O(\TX_CRC[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6996FFFF69960000)) 
    \TX_CRC[9]_i_1 
       (.I0(slv1_out[4]),
        .I1(slv1_out[1]),
        .I2(p_18_in[1]),
        .I3(\TX_CRC[9]_i_2_n_0 ),
        .I4(\TX_PHY_STATE_reg_n_0_[2] ),
        .I5(\TX_CRC[9]_i_3_n_0 ),
        .O(\TX_CRC[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[9]_i_2 
       (.I0(slv1_out[2]),
        .I1(p_17_in[1]),
        .I2(slv1_out[5]),
        .I3(p_1_in126_in),
        .I4(p_18_in[0]),
        .I5(p_16_in[0]),
        .O(\TX_CRC[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \TX_CRC[9]_i_3 
       (.I0(\TX_CRC[9]_i_4_n_0 ),
        .I1(p_1_in126_in),
        .I2(slv1_out[5]),
        .I3(p_21_in[1]),
        .I4(slv1_out[2]),
        .I5(\TX_CRC[27]_i_4_n_0 ),
        .O(\TX_CRC[9]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \TX_CRC[9]_i_4 
       (.I0(slv1_out[4]),
        .I1(slv1_out[1]),
        .I2(p_22_in[1]),
        .O(\TX_CRC[9]_i_4_n_0 ));
  FDSE \TX_CRC_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[0]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[0] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[10]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[10] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[10]_i_1 
       (.I0(NEXTCRC32_D80189_out),
        .I1(\TX_CRC[10]_i_3_n_0 ),
        .O(\TX_CRC_reg[10]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[11]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[11] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[12] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[12]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[12] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[12]_i_1 
       (.I0(\TX_CRC[12]_i_2_n_0 ),
        .I1(\TX_CRC[12]_i_3_n_0 ),
        .O(\TX_CRC_reg[12]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[13] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[13]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[13] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[13]_i_1 
       (.I0(NEXTCRC32_D80195_out),
        .I1(\TX_CRC[13]_i_3_n_0 ),
        .O(\TX_CRC_reg[13]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[14] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[14]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[14] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[14]_i_1 
       (.I0(\TX_CRC[14]_i_2_n_0 ),
        .I1(\TX_CRC[14]_i_3_n_0 ),
        .O(\TX_CRC_reg[14]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[15] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[15]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[15] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[16] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[16]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[16] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[17] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[17]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[17] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[17]_i_1 
       (.I0(NEXTCRC32_D80203_out),
        .I1(\TX_CRC[17]_i_3_n_0 ),
        .O(\TX_CRC_reg[17]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[18] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[18]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[18] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[18]_i_1 
       (.I0(\TX_CRC[18]_i_2_n_0 ),
        .I1(\TX_CRC[18]_i_3_n_0 ),
        .O(\TX_CRC_reg[18]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[19] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[19]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[19] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[1]_i_1_n_0 ),
        .Q(p_1_in126_in),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[1]_i_1 
       (.I0(\TX_CRC[1]_i_2_n_0 ),
        .I1(NEXTCRC32_D8070_out),
        .O(\TX_CRC_reg[1]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[20] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[20]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[20] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[21] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[21]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[21] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[22] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[22]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[22] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[23] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[23]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[23] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[24] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[24]_i_1_n_0 ),
        .Q(slv1_out[0]),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[24]_i_1 
       (.I0(NEXTCRC32_D80217_out),
        .I1(\TX_CRC[24]_i_3_n_0 ),
        .O(\TX_CRC_reg[24]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[25] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[25]_i_1_n_0 ),
        .Q(slv1_out[1]),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[25]_i_1 
       (.I0(\TX_CRC[25]_i_2_n_0 ),
        .I1(\TX_CRC[25]_i_3_n_0 ),
        .O(\TX_CRC_reg[25]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[26] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[26]_i_1_n_0 ),
        .Q(slv1_out[2]),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[27] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[27]_i_1_n_0 ),
        .Q(slv1_out[3]),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[28] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[28]_i_1_n_0 ),
        .Q(slv1_out[4]),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[29] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[29]_i_1_n_0 ),
        .Q(slv1_out[5]),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[29]_i_1 
       (.I0(\TX_CRC[29]_i_2_n_0 ),
        .I1(\TX_CRC[29]_i_3_n_0 ),
        .O(\TX_CRC_reg[29]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[2]_i_1_n_0 ),
        .Q(p_1_in128_in),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[30] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[30]_i_1_n_0 ),
        .Q(slv1_out[6]),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[30]_i_1 
       (.I0(\TX_CRC[30]_i_2_n_0 ),
        .I1(\TX_CRC[30]_i_3_n_0 ),
        .O(\TX_CRC_reg[30]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[31] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[31]_i_3_n_0 ),
        .Q(slv1_out[7]),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[3]_i_1_n_0 ),
        .Q(p_1_in130_in),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[3]_i_1 
       (.I0(NEXTCRC32_D80177_out),
        .I1(\TX_CRC[3]_i_3_n_0 ),
        .O(\TX_CRC_reg[3]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[4]_i_1_n_0 ),
        .Q(p_1_in132_in),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[4]_i_1 
       (.I0(\TX_CRC[4]_i_2_n_0 ),
        .I1(\TX_CRC[4]_i_3_n_0 ),
        .O(\TX_CRC_reg[4]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[5]_i_1_n_0 ),
        .Q(p_1_in133_in),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[5]_i_1 
       (.I0(NEXTCRC32_D80181_out),
        .I1(NEXTCRC32_D8074_out),
        .O(\TX_CRC_reg[5]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC_reg[6]_i_1_n_0 ),
        .Q(p_1_in135_in),
        .S(\TX_CRC[31]_i_1_n_0 ));
  MUXF7 \TX_CRC_reg[6]_i_1 
       (.I0(\TX_CRC[6]_i_2_n_0 ),
        .I1(\TX_CRC[6]_i_3_n_0 ),
        .O(\TX_CRC_reg[6]_i_1_n_0 ),
        .S(\TX_PHY_STATE_reg_n_0_[2] ));
  FDSE \TX_CRC_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[7]_i_1_n_0 ),
        .Q(p_1_in136_in),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[8]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[8] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  FDSE \TX_CRC_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_CRC[31]_i_2_n_0 ),
        .D(\TX_CRC[9]_i_1_n_0 ),
        .Q(\TX_CRC_reg_n_0_[9] ),
        .S(\TX_CRC[31]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \TX_IN_COUNT[10]_i_1 
       (.I0(S_TX_ACK_reg_n_0),
        .I1(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I2(\TX_PACKET_STATE_reg_n_0_[0] ),
        .O(\TX_IN_COUNT[10]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0444)) 
    \TX_IN_COUNT[10]_i_2 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(S_TX_ACK_reg_n_0),
        .I2(\TX_PACKET_STATE_reg_n_0_[0] ),
        .I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
        .O(\TX_IN_COUNT[10]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT5 #(
    .INIT(32'hAAAA6AAA)) 
    \TX_IN_COUNT[10]_i_3 
       (.I0(TX_IN_COUNT[10]),
        .I1(TX_IN_COUNT[9]),
        .I2(TX_IN_COUNT[8]),
        .I3(TX_IN_COUNT[7]),
        .I4(\TX_IN_COUNT[10]_i_4_n_0 ),
        .O(\TX_IN_COUNT[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \TX_IN_COUNT[10]_i_4 
       (.I0(TX_IN_COUNT[5]),
        .I1(TX_IN_COUNT[3]),
        .I2(TX_IN_COUNT[1]),
        .I3(TX_IN_COUNT[2]),
        .I4(TX_IN_COUNT[4]),
        .I5(TX_IN_COUNT[6]),
        .O(\TX_IN_COUNT[10]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT5 #(
    .INIT(32'hFFBF0444)) 
    \TX_IN_COUNT[1]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(S_TX_ACK_reg_n_0),
        .I2(\TX_PACKET_STATE_reg_n_0_[0] ),
        .I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
        .I4(TX_IN_COUNT[1]),
        .O(\TX_IN_COUNT[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCFDFCF00002000)) 
    \TX_IN_COUNT[2]_i_1 
       (.I0(TX_IN_COUNT[1]),
        .I1(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I2(S_TX_ACK_reg_n_0),
        .I3(\TX_PACKET_STATE_reg_n_0_[0] ),
        .I4(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
        .I5(TX_IN_COUNT[2]),
        .O(\TX_IN_COUNT[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \TX_IN_COUNT[3]_i_1 
       (.I0(TX_IN_COUNT[3]),
        .I1(TX_IN_COUNT[2]),
        .I2(TX_IN_COUNT[1]),
        .O(\TX_IN_COUNT[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \TX_IN_COUNT[4]_i_1 
       (.I0(TX_IN_COUNT[4]),
        .I1(TX_IN_COUNT[3]),
        .I2(TX_IN_COUNT[1]),
        .I3(TX_IN_COUNT[2]),
        .O(\TX_IN_COUNT[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \TX_IN_COUNT[5]_i_1 
       (.I0(TX_IN_COUNT[5]),
        .I1(TX_IN_COUNT[4]),
        .I2(TX_IN_COUNT[2]),
        .I3(TX_IN_COUNT[1]),
        .I4(TX_IN_COUNT[3]),
        .O(\TX_IN_COUNT[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \TX_IN_COUNT[6]_i_1 
       (.I0(TX_IN_COUNT[6]),
        .I1(TX_IN_COUNT[5]),
        .I2(TX_IN_COUNT[3]),
        .I3(TX_IN_COUNT[1]),
        .I4(TX_IN_COUNT[2]),
        .I5(TX_IN_COUNT[4]),
        .O(\TX_IN_COUNT[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \TX_IN_COUNT[7]_i_1 
       (.I0(TX_IN_COUNT[7]),
        .I1(\TX_IN_COUNT[10]_i_4_n_0 ),
        .O(\TX_IN_COUNT[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT3 #(
    .INIT(8'hA6)) 
    \TX_IN_COUNT[8]_i_1 
       (.I0(TX_IN_COUNT[8]),
        .I1(TX_IN_COUNT[7]),
        .I2(\TX_IN_COUNT[10]_i_4_n_0 ),
        .O(\TX_IN_COUNT[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT4 #(
    .INIT(16'h9AAA)) 
    \TX_IN_COUNT[9]_i_1 
       (.I0(TX_IN_COUNT[9]),
        .I1(\TX_IN_COUNT[10]_i_4_n_0 ),
        .I2(TX_IN_COUNT[7]),
        .I3(TX_IN_COUNT[8]),
        .O(\TX_IN_COUNT[9]_i_1_n_0 ));
  FDRE \TX_IN_COUNT_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_IN_COUNT[10]_i_2_n_0 ),
        .D(\TX_IN_COUNT[10]_i_3_n_0 ),
        .Q(TX_IN_COUNT[10]),
        .R(\TX_IN_COUNT[10]_i_1_n_0 ));
  FDRE \TX_IN_COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\TX_IN_COUNT[1]_i_1_n_0 ),
        .Q(TX_IN_COUNT[1]),
        .R(1'b0));
  FDRE \TX_IN_COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\TX_IN_COUNT[2]_i_1_n_0 ),
        .Q(TX_IN_COUNT[2]),
        .R(1'b0));
  FDRE \TX_IN_COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_IN_COUNT[10]_i_2_n_0 ),
        .D(\TX_IN_COUNT[3]_i_1_n_0 ),
        .Q(TX_IN_COUNT[3]),
        .R(\TX_IN_COUNT[10]_i_1_n_0 ));
  FDRE \TX_IN_COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_IN_COUNT[10]_i_2_n_0 ),
        .D(\TX_IN_COUNT[4]_i_1_n_0 ),
        .Q(TX_IN_COUNT[4]),
        .R(\TX_IN_COUNT[10]_i_1_n_0 ));
  FDRE \TX_IN_COUNT_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_IN_COUNT[10]_i_2_n_0 ),
        .D(\TX_IN_COUNT[5]_i_1_n_0 ),
        .Q(TX_IN_COUNT[5]),
        .R(\TX_IN_COUNT[10]_i_1_n_0 ));
  FDRE \TX_IN_COUNT_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_IN_COUNT[10]_i_2_n_0 ),
        .D(\TX_IN_COUNT[6]_i_1_n_0 ),
        .Q(TX_IN_COUNT[6]),
        .R(\TX_IN_COUNT[10]_i_1_n_0 ));
  FDRE \TX_IN_COUNT_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_IN_COUNT[10]_i_2_n_0 ),
        .D(\TX_IN_COUNT[7]_i_1_n_0 ),
        .Q(TX_IN_COUNT[7]),
        .R(\TX_IN_COUNT[10]_i_1_n_0 ));
  FDRE \TX_IN_COUNT_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_IN_COUNT[10]_i_2_n_0 ),
        .D(\TX_IN_COUNT[8]_i_1_n_0 ),
        .Q(TX_IN_COUNT[8]),
        .R(\TX_IN_COUNT[10]_i_1_n_0 ));
  FDRE \TX_IN_COUNT_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_IN_COUNT[10]_i_2_n_0 ),
        .D(\TX_IN_COUNT[9]_i_1_n_0 ),
        .Q(TX_IN_COUNT[9]),
        .R(\TX_IN_COUNT[10]_i_1_n_0 ));
  (* IS_CLOCK_GATED *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* POWER_OPTED_CE = "ENBWREN=NEW" *) 
  (* RTL_RAM_BITS = "16400" *) 
  (* RTL_RAM_NAME = "TX_MEMORY" *) 
  (* bram_addr_begin = "0" *) 
  (* bram_addr_end = "2047" *) 
  (* bram_slice_begin = "0" *) 
  (* bram_slice_end = "17" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    TX_MEMORY_reg
       (.ADDRARDADDR({1'b1,TX_WRITE_ADDRESS_DEL,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,TX_READ_ADDRESS,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b1),
        .CASCADEINB(1'b1),
        .CASCADEOUTA(NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED),
        .CASCADEOUTB(NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED),
        .CLKARDCLK(ETH_CLK_OBUF),
        .CLKBWRCLK(ETH_CLK_OBUF),
        .DBITERR(NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(NLW_TX_MEMORY_reg_DOADO_UNCONNECTED[31:0]),
        .DOBDO({NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED[31:16],p_20_in,p_21_in,p_22_in,p_0_in167_in,TX_MEMORY_reg_n_59,p_16_in,p_17_in,p_18_in,p_0_in66_in,TX_MEMORY_reg_n_67}),
        .DOPADOP(NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED[3:0]),
        .DOPBDOP(NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED[3:0]),
        .ECCPARITY(NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED[7:0]),
        .ENARDEN(TX_WRITE),
        .ENBWREN(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9),
        .INJECTDBITERR(NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED),
        .INJECTSBITERR(NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED),
        .RDADDRECC(NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED),
        .REGCEB(NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED),
        .WEA({1'b0,1'b0,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
  LUT4 #(
    .INIT(16'hff35)) 
    TX_MEMORY_reg_ENBWREN_cooolgate_en_gate_17
       (.I0(\TX_PHY_STATE_reg_n_0_[4] ),
        .I1(\TX_PHY_STATE[4]_i_2_n_0 ),
        .I2(\TX_PHY_STATE[4]_i_1_n_0 ),
        .I3(INTERNAL_RST_reg),
        .O(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \TX_OUT_COUNT[0]_i_1 
       (.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
        .I1(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(TX_OUT_COUNT0_in));
  LUT6 #(
    .INIT(64'h00000000AA100010)) 
    \TX_OUT_COUNT[10]_i_1 
       (.I0(\TX_PHY_STATE_reg_n_0_[3] ),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(GO_SYNC),
        .I3(\TX_PHY_STATE_reg_n_0_[0] ),
        .I4(\TX_OUT_COUNT[10]_i_3_n_0 ),
        .I5(\TX_OUT_COUNT[10]_i_4_n_0 ),
        .O(\TX_OUT_COUNT[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT4 #(
    .INIT(16'hE133)) 
    \TX_OUT_COUNT[10]_i_2 
       (.I0(\TX_OUT_COUNT_reg_n_0_[9] ),
        .I1(\TX_OUT_COUNT[10]_i_5_n_0 ),
        .I2(\TX_OUT_COUNT_reg_n_0_[10] ),
        .I3(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF7F)) 
    \TX_OUT_COUNT[10]_i_3 
       (.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
        .I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
        .I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
        .I3(\TX_OUT_COUNT_reg_n_0_[0] ),
        .I4(\TX_OUT_COUNT_reg_n_0_[1] ),
        .I5(\TX_OUT_COUNT_reg_n_0_[2] ),
        .O(\TX_OUT_COUNT[10]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_OUT_COUNT[10]_i_4 
       (.I0(\TX_PHY_STATE_reg_n_0_[1] ),
        .I1(\TX_PHY_STATE_reg_n_0_[4] ),
        .O(\TX_OUT_COUNT[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEF0F0F0F0)) 
    \TX_OUT_COUNT[10]_i_5 
       (.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[5] ),
        .I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
        .I3(\TX_OUT_COUNT_reg_n_0_[6] ),
        .I4(\TX_OUT_COUNT_reg_n_0_[8] ),
        .I5(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[10]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \TX_OUT_COUNT[10]_i_6 
       (.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[4] ),
        .I2(\TX_OUT_COUNT_reg_n_0_[5] ),
        .O(\TX_OUT_COUNT[10]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \TX_OUT_COUNT[10]_i_7 
       (.I0(\TX_OUT_COUNT_reg_n_0_[10] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[9] ),
        .O(\TX_OUT_COUNT[10]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \TX_OUT_COUNT[10]_i_8 
       (.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[8] ),
        .I2(\TX_OUT_COUNT_reg_n_0_[7] ),
        .O(\TX_OUT_COUNT[10]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT3 #(
    .INIT(8'h9F)) 
    \TX_OUT_COUNT[1]_i_1 
       (.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[1] ),
        .I2(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT4 #(
    .INIT(16'hE1FF)) 
    \TX_OUT_COUNT[2]_i_1 
       (.I0(\TX_OUT_COUNT_reg_n_0_[1] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[0] ),
        .I2(\TX_OUT_COUNT_reg_n_0_[2] ),
        .I3(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT5 #(
    .INIT(32'hFE01FFFF)) 
    \TX_OUT_COUNT[3]_i_1 
       (.I0(\TX_OUT_COUNT_reg_n_0_[2] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[0] ),
        .I2(\TX_OUT_COUNT_reg_n_0_[1] ),
        .I3(\TX_OUT_COUNT_reg_n_0_[3] ),
        .I4(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFE0001FFFFFFFF)) 
    \TX_OUT_COUNT[4]_i_1 
       (.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[1] ),
        .I2(\TX_OUT_COUNT_reg_n_0_[0] ),
        .I3(\TX_OUT_COUNT_reg_n_0_[2] ),
        .I4(\TX_OUT_COUNT_reg_n_0_[4] ),
        .I5(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \TX_OUT_COUNT[5]_i_1 
       (.I0(\TX_OUT_COUNT[8]_i_2_n_0 ),
        .I1(\TX_OUT_COUNT_reg_n_0_[5] ),
        .I2(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT4 #(
    .INIT(16'hE133)) 
    \TX_OUT_COUNT[6]_i_1 
       (.I0(\TX_OUT_COUNT_reg_n_0_[5] ),
        .I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
        .I2(\TX_OUT_COUNT_reg_n_0_[6] ),
        .I3(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT5 #(
    .INIT(32'hFE013333)) 
    \TX_OUT_COUNT[7]_i_1 
       (.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
        .I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
        .I2(\TX_OUT_COUNT_reg_n_0_[5] ),
        .I3(\TX_OUT_COUNT_reg_n_0_[7] ),
        .I4(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFE00010F0F0F0F)) 
    \TX_OUT_COUNT[8]_i_1 
       (.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[5] ),
        .I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
        .I3(\TX_OUT_COUNT_reg_n_0_[6] ),
        .I4(\TX_OUT_COUNT_reg_n_0_[8] ),
        .I5(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000000)) 
    \TX_OUT_COUNT[8]_i_2 
       (.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
        .I1(\TX_OUT_COUNT_reg_n_0_[1] ),
        .I2(\TX_OUT_COUNT_reg_n_0_[0] ),
        .I3(\TX_OUT_COUNT_reg_n_0_[2] ),
        .I4(\TX_OUT_COUNT_reg_n_0_[4] ),
        .I5(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \TX_OUT_COUNT[9]_i_1 
       (.I0(\TX_OUT_COUNT[10]_i_5_n_0 ),
        .I1(\TX_OUT_COUNT_reg_n_0_[9] ),
        .I2(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_OUT_COUNT[9]_i_1_n_0 ));
  FDRE \TX_OUT_COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(TX_OUT_COUNT0_in),
        .Q(\TX_OUT_COUNT_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[10]_i_2_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[1]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[2]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[3]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[4]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[5]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[6]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[7]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[8]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \TX_OUT_COUNT_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
        .D(\TX_OUT_COUNT[9]_i_1_n_0 ),
        .Q(\TX_OUT_COUNT_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT5 #(
    .INIT(32'hFF007C7C)) 
    \TX_PACKET_STATE[0]_i_1 
       (.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
        .I1(\TX_PACKET_STATE_reg_n_0_[0] ),
        .I2(S_TX_ACK_reg_n_0),
        .I3(DONE_SYNC),
        .I4(\TX_PACKET_STATE_reg_n_0_[1] ),
        .O(\TX_PACKET_STATE[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT5 #(
    .INIT(32'hFF338080)) 
    \TX_PACKET_STATE[1]_i_1 
       (.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
        .I1(\TX_PACKET_STATE_reg_n_0_[0] ),
        .I2(S_TX_ACK_reg_n_0),
        .I3(DONE_SYNC),
        .I4(\TX_PACKET_STATE_reg_n_0_[1] ),
        .O(\TX_PACKET_STATE[1]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \TX_PACKET_STATE[1]_i_10 
       (.I0(TX_IN_COUNT[6]),
        .I1(TX_IN_COUNT[7]),
        .O(\TX_PACKET_STATE[1]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \TX_PACKET_STATE[1]_i_11 
       (.I0(TX_IN_COUNT[4]),
        .I1(TX_IN_COUNT[5]),
        .O(\TX_PACKET_STATE[1]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \TX_PACKET_STATE[1]_i_12 
       (.I0(TX_IN_COUNT[2]),
        .I1(TX_IN_COUNT[3]),
        .O(\TX_PACKET_STATE[1]_i_12_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TX_PACKET_STATE[1]_i_13 
       (.I0(TX_IN_COUNT[1]),
        .O(\TX_PACKET_STATE[1]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_PACKET_STATE[1]_i_4 
       (.I0(TX_IN_COUNT[9]),
        .I1(TX_IN_COUNT[8]),
        .O(\TX_PACKET_STATE[1]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TX_PACKET_STATE[1]_i_5 
       (.I0(TX_IN_COUNT[10]),
        .O(\TX_PACKET_STATE[1]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \TX_PACKET_STATE[1]_i_6 
       (.I0(TX_IN_COUNT[8]),
        .I1(TX_IN_COUNT[9]),
        .O(\TX_PACKET_STATE[1]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_PACKET_STATE[1]_i_7 
       (.I0(TX_IN_COUNT[7]),
        .I1(TX_IN_COUNT[6]),
        .O(\TX_PACKET_STATE[1]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_PACKET_STATE[1]_i_8 
       (.I0(TX_IN_COUNT[5]),
        .I1(TX_IN_COUNT[4]),
        .O(\TX_PACKET_STATE[1]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_PACKET_STATE[1]_i_9 
       (.I0(TX_IN_COUNT[3]),
        .I1(TX_IN_COUNT[2]),
        .O(\TX_PACKET_STATE[1]_i_9_n_0 ));
  FDRE \TX_PACKET_STATE_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\TX_PACKET_STATE[0]_i_1_n_0 ),
        .Q(\TX_PACKET_STATE_reg_n_0_[0] ),
        .R(INTERNAL_RST_reg));
  FDRE \TX_PACKET_STATE_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(\TX_PACKET_STATE[1]_i_1_n_0 ),
        .Q(\TX_PACKET_STATE_reg_n_0_[1] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \TX_PACKET_STATE_reg[1]_i_2 
       (.CI(\TX_PACKET_STATE_reg[1]_i_3_n_0 ),
        .CO({\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [3:2],\TX_PACKET_STATE_reg[1]_i_2_n_2 ,\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,TX_IN_COUNT[10],\TX_PACKET_STATE[1]_i_4_n_0 }),
        .O(\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED [3:0]),
        .S({1'b0,1'b0,\TX_PACKET_STATE[1]_i_5_n_0 ,\TX_PACKET_STATE[1]_i_6_n_0 }));
  CARRY4 \TX_PACKET_STATE_reg[1]_i_3 
       (.CI(1'b0),
        .CO({\TX_PACKET_STATE_reg[1]_i_3_n_0 ,\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b1),
        .DI({\TX_PACKET_STATE[1]_i_7_n_0 ,\TX_PACKET_STATE[1]_i_8_n_0 ,\TX_PACKET_STATE[1]_i_9_n_0 ,TX_IN_COUNT[1]}),
        .O(\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED [3:0]),
        .S({\TX_PACKET_STATE[1]_i_10_n_0 ,\TX_PACKET_STATE[1]_i_11_n_0 ,\TX_PACKET_STATE[1]_i_12_n_0 ,\TX_PACKET_STATE[1]_i_13_n_0 }));
  LUT6 #(
    .INIT(64'h80000000DFFFFFFF)) 
    \TX_PHY_STATE[0]_i_1 
       (.I0(\TX_PHY_STATE_reg_n_0_[2] ),
        .I1(GO_SYNC),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(\TX_PHY_STATE_reg_n_0_[3] ),
        .I4(\TX_PHY_STATE_reg_n_0_[4] ),
        .I5(\TX_PHY_STATE_reg_n_0_[0] ),
        .O(\TX_PHY_STATE[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000FFFFDFFF0000)) 
    \TX_PHY_STATE[1]_i_1 
       (.I0(\TX_PHY_STATE_reg_n_0_[2] ),
        .I1(GO_SYNC),
        .I2(\TX_PHY_STATE_reg_n_0_[3] ),
        .I3(\TX_PHY_STATE_reg_n_0_[4] ),
        .I4(\TX_PHY_STATE_reg_n_0_[1] ),
        .I5(\TX_PHY_STATE_reg_n_0_[0] ),
        .O(\TX_PHY_STATE[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8ABABA8ABA8ABA8A)) 
    \TX_PHY_STATE[2]_i_1 
       (.I0(\TX_PHY_STATE[2]_i_2_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[3] ),
        .I2(\TX_PHY_STATE_reg_n_0_[4] ),
        .I3(\TX_PHY_STATE_reg_n_0_[2] ),
        .I4(\TX_PHY_STATE_reg_n_0_[0] ),
        .I5(\TX_PHY_STATE_reg_n_0_[1] ),
        .O(\TX_PHY_STATE[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8BB88BBBB8888)) 
    \TX_PHY_STATE[2]_i_2 
       (.I0(\TX_PHY_STATE[2]_i_3_n_0 ),
        .I1(\TX_PHY_STATE[2]_i_4_n_0 ),
        .I2(GO_SYNC),
        .I3(\TX_PHY_STATE_reg_n_0_[0] ),
        .I4(\TX_PHY_STATE_reg_n_0_[2] ),
        .I5(\TX_PHY_STATE_reg_n_0_[1] ),
        .O(\TX_PHY_STATE[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0FF0F8F0)) 
    \TX_PHY_STATE[2]_i_3 
       (.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[3] ),
        .I2(\TX_PHY_STATE_reg_n_0_[2] ),
        .I3(\TX_PHY_STATE_reg_n_0_[0] ),
        .I4(\TX_PHY_STATE_reg_n_0_[1] ),
        .O(\TX_PHY_STATE[2]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h5D)) 
    \TX_PHY_STATE[2]_i_4 
       (.I0(\TX_PHY_STATE_reg_n_0_[4] ),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_PHY_STATE[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hCFAAC0AAC0AAC0AA)) 
    \TX_PHY_STATE[3]_i_1 
       (.I0(\TX_PHY_STATE[3]_i_2_n_0 ),
        .I1(\TX_PHY_STATE[3]_i_3_n_0 ),
        .I2(\TX_PHY_STATE_reg_n_0_[3] ),
        .I3(\TX_PHY_STATE_reg_n_0_[4] ),
        .I4(\TX_PHY_STATE_reg_n_0_[2] ),
        .I5(\TX_PHY_STATE[3]_i_4_n_0 ),
        .O(\TX_PHY_STATE[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h3CCC8CCC)) 
    \TX_PHY_STATE[3]_i_2 
       (.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
        .I1(\TX_PHY_STATE_reg_n_0_[3] ),
        .I2(\TX_PHY_STATE_reg_n_0_[2] ),
        .I3(\TX_PHY_STATE_reg_n_0_[0] ),
        .I4(\TX_PHY_STATE_reg_n_0_[1] ),
        .O(\TX_PHY_STATE[3]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hBF)) 
    \TX_PHY_STATE[3]_i_3 
       (.I0(GO_SYNC),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .O(\TX_PHY_STATE[3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \TX_PHY_STATE[3]_i_4 
       (.I0(\TX_PHY_STATE_reg_n_0_[1] ),
        .I1(\TX_PHY_STATE_reg_n_0_[0] ),
        .O(\TX_PHY_STATE[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \TX_PHY_STATE[3]_i_5 
       (.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
        .I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
        .I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
        .I3(\TX_OUT_COUNT_reg_n_0_[0] ),
        .I4(\TX_OUT_COUNT_reg_n_0_[1] ),
        .I5(\TX_OUT_COUNT_reg_n_0_[2] ),
        .O(\TX_PHY_STATE[3]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hAFBEAABE)) 
    \TX_PHY_STATE[4]_i_1 
       (.I0(\TX_PHY_STATE[4]_i_3_n_0 ),
        .I1(GO_SYNC),
        .I2(\TX_PHY_STATE_reg_n_0_[1] ),
        .I3(\TX_PHY_STATE_reg_n_0_[0] ),
        .I4(\TX_PHY_STATE[4]_i_4_n_0 ),
        .O(\TX_PHY_STATE[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF5FF8800FFFF0000)) 
    \TX_PHY_STATE[4]_i_2 
       (.I0(\TX_PHY_STATE_reg_n_0_[1] ),
        .I1(\TX_PHY_STATE_reg_n_0_[0] ),
        .I2(GO_SYNC),
        .I3(\TX_PHY_STATE_reg_n_0_[2] ),
        .I4(\TX_PHY_STATE_reg_n_0_[4] ),
        .I5(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_PHY_STATE[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7FFE)) 
    \TX_PHY_STATE[4]_i_3 
       (.I0(\TX_PHY_STATE_reg_n_0_[1] ),
        .I1(\TX_PHY_STATE_reg_n_0_[2] ),
        .I2(\TX_PHY_STATE_reg_n_0_[3] ),
        .I3(\TX_PHY_STATE_reg_n_0_[4] ),
        .O(\TX_PHY_STATE[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \TX_PHY_STATE[4]_i_4 
       (.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
        .I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
        .I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
        .I3(\PREAMBLE_COUNT_reg_n_0_[4] ),
        .I4(\PREAMBLE_COUNT_reg_n_0_[2] ),
        .O(\TX_PHY_STATE[4]_i_4_n_0 ));
  FDRE \TX_PHY_STATE_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_PHY_STATE[4]_i_1_n_0 ),
        .D(\TX_PHY_STATE[0]_i_1_n_0 ),
        .Q(\TX_PHY_STATE_reg_n_0_[0] ),
        .R(INTERNAL_RST_reg));
  FDRE \TX_PHY_STATE_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_PHY_STATE[4]_i_1_n_0 ),
        .D(\TX_PHY_STATE[1]_i_1_n_0 ),
        .Q(\TX_PHY_STATE_reg_n_0_[1] ),
        .R(INTERNAL_RST_reg));
  FDRE \TX_PHY_STATE_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_PHY_STATE[4]_i_1_n_0 ),
        .D(\TX_PHY_STATE[2]_i_1_n_0 ),
        .Q(\TX_PHY_STATE_reg_n_0_[2] ),
        .R(INTERNAL_RST_reg));
  FDRE \TX_PHY_STATE_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_PHY_STATE[4]_i_1_n_0 ),
        .D(\TX_PHY_STATE[3]_i_1_n_0 ),
        .Q(\TX_PHY_STATE_reg_n_0_[3] ),
        .R(INTERNAL_RST_reg));
  FDRE \TX_PHY_STATE_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_PHY_STATE[4]_i_1_n_0 ),
        .D(\TX_PHY_STATE[4]_i_2_n_0 ),
        .Q(\TX_PHY_STATE_reg_n_0_[4] ),
        .R(INTERNAL_RST_reg));
  FDRE \TX_READ_ADDRESS_reg_rep[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ),
        .Q(TX_READ_ADDRESS[0]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[10]),
        .Q(TX_READ_ADDRESS[10]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[1]),
        .Q(TX_READ_ADDRESS[1]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[2]),
        .Q(TX_READ_ADDRESS[2]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[3]),
        .Q(TX_READ_ADDRESS[3]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[4]),
        .Q(TX_READ_ADDRESS[4]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[5]),
        .Q(TX_READ_ADDRESS[5]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[6]),
        .Q(TX_READ_ADDRESS[6]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[7]),
        .Q(TX_READ_ADDRESS[7]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[8]),
        .Q(TX_READ_ADDRESS[8]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  FDRE \TX_READ_ADDRESS_reg_rep[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
        .D(TX_READ_ADDRESS0[9]),
        .Q(TX_READ_ADDRESS[9]),
        .R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \TX_READ_ADDRESS_rep[0]_i_1 
       (.I0(TX_READ_ADDRESS[0]),
        .O(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \TX_READ_ADDRESS_rep[10]_i_1 
       (.I0(TX_READ_ADDRESS[8]),
        .I1(TX_READ_ADDRESS[6]),
        .I2(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
        .I3(TX_READ_ADDRESS[7]),
        .I4(TX_READ_ADDRESS[9]),
        .I5(TX_READ_ADDRESS[10]),
        .O(TX_READ_ADDRESS0[10]));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \TX_READ_ADDRESS_rep[1]_i_1 
       (.I0(TX_READ_ADDRESS[0]),
        .I1(TX_READ_ADDRESS[1]),
        .O(TX_READ_ADDRESS0[1]));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \TX_READ_ADDRESS_rep[2]_i_1 
       (.I0(TX_READ_ADDRESS[0]),
        .I1(TX_READ_ADDRESS[1]),
        .I2(TX_READ_ADDRESS[2]),
        .O(TX_READ_ADDRESS0[2]));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \TX_READ_ADDRESS_rep[3]_i_1 
       (.I0(TX_READ_ADDRESS[1]),
        .I1(TX_READ_ADDRESS[0]),
        .I2(TX_READ_ADDRESS[2]),
        .I3(TX_READ_ADDRESS[3]),
        .O(TX_READ_ADDRESS0[3]));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \TX_READ_ADDRESS_rep[4]_i_1 
       (.I0(TX_READ_ADDRESS[2]),
        .I1(TX_READ_ADDRESS[0]),
        .I2(TX_READ_ADDRESS[1]),
        .I3(TX_READ_ADDRESS[3]),
        .I4(TX_READ_ADDRESS[4]),
        .O(TX_READ_ADDRESS0[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \TX_READ_ADDRESS_rep[5]_i_1 
       (.I0(TX_READ_ADDRESS[3]),
        .I1(TX_READ_ADDRESS[1]),
        .I2(TX_READ_ADDRESS[0]),
        .I3(TX_READ_ADDRESS[2]),
        .I4(TX_READ_ADDRESS[4]),
        .I5(TX_READ_ADDRESS[5]),
        .O(TX_READ_ADDRESS0[5]));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \TX_READ_ADDRESS_rep[6]_i_1 
       (.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
        .I1(TX_READ_ADDRESS[6]),
        .O(TX_READ_ADDRESS0[6]));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \TX_READ_ADDRESS_rep[7]_i_1 
       (.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
        .I1(TX_READ_ADDRESS[6]),
        .I2(TX_READ_ADDRESS[7]),
        .O(TX_READ_ADDRESS0[7]));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \TX_READ_ADDRESS_rep[8]_i_1 
       (.I0(TX_READ_ADDRESS[6]),
        .I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
        .I2(TX_READ_ADDRESS[7]),
        .I3(TX_READ_ADDRESS[8]),
        .O(TX_READ_ADDRESS0[8]));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \TX_READ_ADDRESS_rep[9]_i_1 
       (.I0(\TX_PHY_STATE_reg_n_0_[2] ),
        .I1(GO_SYNC),
        .I2(\TX_PHY_STATE_reg_n_0_[4] ),
        .I3(\TX_PHY_STATE_reg_n_0_[0] ),
        .I4(\TX_PHY_STATE_reg_n_0_[1] ),
        .I5(\TX_PHY_STATE_reg_n_0_[3] ),
        .O(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0100010000010000)) 
    \TX_READ_ADDRESS_rep[9]_i_2 
       (.I0(\TX_PHY_STATE_reg_n_0_[1] ),
        .I1(\TX_PHY_STATE_reg_n_0_[0] ),
        .I2(\TX_PHY_STATE_reg_n_0_[4] ),
        .I3(\TX_PHY_STATE_reg_n_0_[3] ),
        .I4(GO_SYNC),
        .I5(\TX_PHY_STATE_reg_n_0_[2] ),
        .O(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \TX_READ_ADDRESS_rep[9]_i_3 
       (.I0(TX_READ_ADDRESS[7]),
        .I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
        .I2(TX_READ_ADDRESS[6]),
        .I3(TX_READ_ADDRESS[8]),
        .I4(TX_READ_ADDRESS[9]),
        .O(TX_READ_ADDRESS0[9]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \TX_READ_ADDRESS_rep[9]_i_4 
       (.I0(TX_READ_ADDRESS[5]),
        .I1(TX_READ_ADDRESS[3]),
        .I2(TX_READ_ADDRESS[1]),
        .I3(TX_READ_ADDRESS[0]),
        .I4(TX_READ_ADDRESS[2]),
        .I5(TX_READ_ADDRESS[4]),
        .O(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \TX_WRITE_ADDRESS[0]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(TX_WRITE_ADDRESS[0]),
        .O(\TX_WRITE_ADDRESS[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h04F0)) 
    \TX_WRITE_ADDRESS[10]_i_1 
       (.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
        .I1(S_TX_ACK_reg_n_0),
        .I2(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I3(\TX_PACKET_STATE_reg_n_0_[0] ),
        .O(\TX_WRITE_ADDRESS[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT4 #(
    .INIT(16'h0078)) 
    \TX_WRITE_ADDRESS[10]_i_2 
       (.I0(\TX_WRITE_ADDRESS[10]_i_3_n_0 ),
        .I1(TX_WRITE_ADDRESS[9]),
        .I2(TX_WRITE_ADDRESS[10]),
        .I3(\TX_PACKET_STATE_reg_n_0_[1] ),
        .O(\TX_WRITE_ADDRESS[10]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0800)) 
    \TX_WRITE_ADDRESS[10]_i_3 
       (.I0(TX_WRITE_ADDRESS[8]),
        .I1(TX_WRITE_ADDRESS[7]),
        .I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
        .I3(TX_WRITE_ADDRESS[6]),
        .O(\TX_WRITE_ADDRESS[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \TX_WRITE_ADDRESS[1]_i_1 
       (.I0(TX_WRITE_ADDRESS[1]),
        .I1(TX_WRITE_ADDRESS[0]),
        .I2(\TX_PACKET_STATE_reg_n_0_[1] ),
        .O(\TX_WRITE_ADDRESS[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'h1540)) 
    \TX_WRITE_ADDRESS[2]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(TX_WRITE_ADDRESS[0]),
        .I2(TX_WRITE_ADDRESS[1]),
        .I3(TX_WRITE_ADDRESS[2]),
        .O(\TX_WRITE_ADDRESS[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT5 #(
    .INIT(32'h15554000)) 
    \TX_WRITE_ADDRESS[3]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(TX_WRITE_ADDRESS[1]),
        .I2(TX_WRITE_ADDRESS[0]),
        .I3(TX_WRITE_ADDRESS[2]),
        .I4(TX_WRITE_ADDRESS[3]),
        .O(\TX_WRITE_ADDRESS[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1555555540000000)) 
    \TX_WRITE_ADDRESS[4]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(TX_WRITE_ADDRESS[2]),
        .I2(TX_WRITE_ADDRESS[0]),
        .I3(TX_WRITE_ADDRESS[1]),
        .I4(TX_WRITE_ADDRESS[3]),
        .I5(TX_WRITE_ADDRESS[4]),
        .O(\TX_WRITE_ADDRESS[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT3 #(
    .INIT(8'h41)) 
    \TX_WRITE_ADDRESS[5]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(\TX_WRITE_ADDRESS[5]_i_2_n_0 ),
        .I2(TX_WRITE_ADDRESS[5]),
        .O(\TX_WRITE_ADDRESS[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \TX_WRITE_ADDRESS[5]_i_2 
       (.I0(TX_WRITE_ADDRESS[3]),
        .I1(TX_WRITE_ADDRESS[1]),
        .I2(TX_WRITE_ADDRESS[0]),
        .I3(TX_WRITE_ADDRESS[2]),
        .I4(TX_WRITE_ADDRESS[4]),
        .O(\TX_WRITE_ADDRESS[5]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h41)) 
    \TX_WRITE_ADDRESS[6]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
        .I2(TX_WRITE_ADDRESS[6]),
        .O(\TX_WRITE_ADDRESS[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'h4510)) 
    \TX_WRITE_ADDRESS[7]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
        .I2(TX_WRITE_ADDRESS[6]),
        .I3(TX_WRITE_ADDRESS[7]),
        .O(\TX_WRITE_ADDRESS[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT5 #(
    .INIT(32'h51550400)) 
    \TX_WRITE_ADDRESS[8]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(TX_WRITE_ADDRESS[6]),
        .I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
        .I3(TX_WRITE_ADDRESS[7]),
        .I4(TX_WRITE_ADDRESS[8]),
        .O(\TX_WRITE_ADDRESS[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5515555500400000)) 
    \TX_WRITE_ADDRESS[9]_i_1 
       (.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I1(TX_WRITE_ADDRESS[8]),
        .I2(TX_WRITE_ADDRESS[7]),
        .I3(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
        .I4(TX_WRITE_ADDRESS[6]),
        .I5(TX_WRITE_ADDRESS[9]),
        .O(\TX_WRITE_ADDRESS[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \TX_WRITE_ADDRESS[9]_i_2 
       (.I0(TX_WRITE_ADDRESS[4]),
        .I1(TX_WRITE_ADDRESS[2]),
        .I2(TX_WRITE_ADDRESS[0]),
        .I3(TX_WRITE_ADDRESS[1]),
        .I4(TX_WRITE_ADDRESS[3]),
        .I5(TX_WRITE_ADDRESS[5]),
        .O(\TX_WRITE_ADDRESS[9]_i_2_n_0 ));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[0]),
        .Q(TX_WRITE_ADDRESS_DEL[0]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[10]),
        .Q(TX_WRITE_ADDRESS_DEL[10]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[1]),
        .Q(TX_WRITE_ADDRESS_DEL[1]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[2]),
        .Q(TX_WRITE_ADDRESS_DEL[2]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[3]),
        .Q(TX_WRITE_ADDRESS_DEL[3]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[4]),
        .Q(TX_WRITE_ADDRESS_DEL[4]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[5]),
        .Q(TX_WRITE_ADDRESS_DEL[5]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[6]),
        .Q(TX_WRITE_ADDRESS_DEL[6]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[7]),
        .Q(TX_WRITE_ADDRESS_DEL[7]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[8]),
        .Q(TX_WRITE_ADDRESS_DEL[8]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_DEL_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_ADDRESS[9]),
        .Q(TX_WRITE_ADDRESS_DEL[9]),
        .R(1'b0));
  FDRE \TX_WRITE_ADDRESS_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[0]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[0]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[10]_i_2_n_0 ),
        .Q(TX_WRITE_ADDRESS[10]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[1]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[1]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[2]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[2]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[3]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[3]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[4]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[4]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[5]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[5]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[6]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[6]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[7]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[7]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[8]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[8]),
        .R(INTERNAL_RST_reg));
  FDRE \TX_WRITE_ADDRESS_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
        .D(\TX_WRITE_ADDRESS[9]_i_1_n_0 ),
        .Q(TX_WRITE_ADDRESS[9]),
        .R(INTERNAL_RST_reg));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'h20)) 
    TX_WRITE_i_1
       (.I0(S_TX_ACK_reg_n_0),
        .I1(\TX_PACKET_STATE_reg_n_0_[1] ),
        .I2(\TX_PACKET_STATE_reg_n_0_[0] ),
        .O(TX_WRITE_i_1_n_0));
  FDRE TX_WRITE_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_WRITE_i_1_n_0),
        .Q(TX_WRITE),
        .R(1'b0));
endmodule

module serial_output
   (IN1_ACK,
    RS232_TX_OBUF,
    INTERNAL_RST_reg,
    ETH_CLK_OBUF,
    IN1_STB,
    Q);
  output IN1_ACK;
  output RS232_TX_OBUF;
  input INTERNAL_RST_reg;
  input ETH_CLK_OBUF;
  input IN1_STB;
  input [7:0]Q;

  wire [11:0]BAUD_COUNT;
  wire \BAUD_COUNT[11]_i_2__0_n_0 ;
  wire \BAUD_COUNT[11]_i_3__0_n_0 ;
  wire \BAUD_COUNT_reg[4]_i_2_n_0 ;
  wire \BAUD_COUNT_reg[8]_i_2_n_0 ;
  wire \BAUD_COUNT_reg_n_0_[0] ;
  wire \BAUD_COUNT_reg_n_0_[10] ;
  wire \BAUD_COUNT_reg_n_0_[11] ;
  wire \BAUD_COUNT_reg_n_0_[1] ;
  wire \BAUD_COUNT_reg_n_0_[2] ;
  wire \BAUD_COUNT_reg_n_0_[3] ;
  wire \BAUD_COUNT_reg_n_0_[4] ;
  wire \BAUD_COUNT_reg_n_0_[5] ;
  wire \BAUD_COUNT_reg_n_0_[6] ;
  wire \BAUD_COUNT_reg_n_0_[7] ;
  wire \BAUD_COUNT_reg_n_0_[8] ;
  wire \BAUD_COUNT_reg_n_0_[9] ;
  wire \DATA[7]_i_1_n_0 ;
  wire \DATA_reg_n_0_[0] ;
  wire ETH_CLK_OBUF;
  wire \FSM_sequential_STATE[0]_i_1_n_0 ;
  wire \FSM_sequential_STATE[1]_i_1_n_0 ;
  wire \FSM_sequential_STATE[2]_i_1_n_0 ;
  wire \FSM_sequential_STATE[3]_i_1_n_0 ;
  wire \FSM_sequential_STATE[3]_i_2_n_0 ;
  wire IN1_ACK;
  wire IN1_STB;
  wire INTERNAL_RST_reg;
  wire [7:0]Q;
  wire RS232_TX_OBUF;
  (* RTL_KEEP = "yes" *) wire [3:0]STATE;
  wire S_IN1_ACK1;
  wire S_IN1_ACK_i_1_n_0;
  wire TX_i_1_n_0;
  wire TX_i_3_n_0;
  wire TX_i_4_n_0;
  wire TX_i_5_n_0;
  wire TX_i_6_n_0;
  wire TX_reg_i_2_n_0;
  wire X16CLK_EN_i_1__0_n_0;
  wire X16CLK_EN_reg_n_0;
  wire [11:1]data0;
  wire p_0_in;
  wire p_1_in;
  wire p_2_in;
  wire p_3_in;
  wire p_4_in;
  wire p_5_in;
  wire p_6_in;
  wire [3:0]\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED ;
  wire [3:3]\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED ;
  wire [2:0]\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED ;
  wire [2:0]\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED ;

  LUT1 #(
    .INIT(2'h1)) 
    \BAUD_COUNT[0]_i_1 
       (.I0(\BAUD_COUNT_reg_n_0_[0] ),
        .O(BAUD_COUNT[0]));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[10]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[10]),
        .O(BAUD_COUNT[10]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[11]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[11]),
        .O(BAUD_COUNT[11]));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    \BAUD_COUNT[11]_i_2__0 
       (.I0(\BAUD_COUNT_reg_n_0_[10] ),
        .I1(\BAUD_COUNT_reg_n_0_[9] ),
        .I2(\BAUD_COUNT_reg_n_0_[6] ),
        .I3(\BAUD_COUNT_reg_n_0_[7] ),
        .I4(\BAUD_COUNT_reg_n_0_[11] ),
        .I5(\BAUD_COUNT_reg_n_0_[5] ),
        .O(\BAUD_COUNT[11]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFDFFF)) 
    \BAUD_COUNT[11]_i_3__0 
       (.I0(\BAUD_COUNT_reg_n_0_[8] ),
        .I1(\BAUD_COUNT_reg_n_0_[1] ),
        .I2(\BAUD_COUNT_reg_n_0_[4] ),
        .I3(\BAUD_COUNT_reg_n_0_[0] ),
        .I4(\BAUD_COUNT_reg_n_0_[2] ),
        .I5(\BAUD_COUNT_reg_n_0_[3] ),
        .O(\BAUD_COUNT[11]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[1]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[1]),
        .O(BAUD_COUNT[1]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[2]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[2]),
        .O(BAUD_COUNT[2]));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[3]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[3]),
        .O(BAUD_COUNT[3]));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[4]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[4]),
        .O(BAUD_COUNT[4]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[5]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[5]),
        .O(BAUD_COUNT[5]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[6]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[6]),
        .O(BAUD_COUNT[6]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[7]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[7]),
        .O(BAUD_COUNT[7]));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[8]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[8]),
        .O(BAUD_COUNT[8]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \BAUD_COUNT[9]_i_1__0 
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .I2(data0[9]),
        .O(BAUD_COUNT[9]));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[0]),
        .Q(\BAUD_COUNT_reg_n_0_[0] ),
        .R(INTERNAL_RST_reg));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[10] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[10]),
        .Q(\BAUD_COUNT_reg_n_0_[10] ),
        .R(INTERNAL_RST_reg));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[11] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[11]),
        .Q(\BAUD_COUNT_reg_n_0_[11] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \BAUD_COUNT_reg[11]_i_4 
       (.CI(\BAUD_COUNT_reg[8]_i_2_n_0 ),
        .CO(\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),
        .S({1'b0,\BAUD_COUNT_reg_n_0_[11] ,\BAUD_COUNT_reg_n_0_[10] ,\BAUD_COUNT_reg_n_0_[9] }));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[1]),
        .Q(\BAUD_COUNT_reg_n_0_[1] ),
        .R(INTERNAL_RST_reg));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[2]),
        .Q(\BAUD_COUNT_reg_n_0_[2] ),
        .R(INTERNAL_RST_reg));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[3]),
        .Q(\BAUD_COUNT_reg_n_0_[3] ),
        .R(INTERNAL_RST_reg));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[4]),
        .Q(\BAUD_COUNT_reg_n_0_[4] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \BAUD_COUNT_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\BAUD_COUNT_reg[4]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(\BAUD_COUNT_reg_n_0_[0] ),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data0[4:1]),
        .S({\BAUD_COUNT_reg_n_0_[4] ,\BAUD_COUNT_reg_n_0_[3] ,\BAUD_COUNT_reg_n_0_[2] ,\BAUD_COUNT_reg_n_0_[1] }));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[5]),
        .Q(\BAUD_COUNT_reg_n_0_[5] ),
        .R(INTERNAL_RST_reg));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[6]),
        .Q(\BAUD_COUNT_reg_n_0_[6] ),
        .R(INTERNAL_RST_reg));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[7]),
        .Q(\BAUD_COUNT_reg_n_0_[7] ),
        .R(INTERNAL_RST_reg));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[8] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[8]),
        .Q(\BAUD_COUNT_reg_n_0_[8] ),
        .R(INTERNAL_RST_reg));
  CARRY4 \BAUD_COUNT_reg[8]_i_2 
       (.CI(\BAUD_COUNT_reg[4]_i_2_n_0 ),
        .CO({\BAUD_COUNT_reg[8]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data0[8:5]),
        .S({\BAUD_COUNT_reg_n_0_[8] ,\BAUD_COUNT_reg_n_0_[7] ,\BAUD_COUNT_reg_n_0_[6] ,\BAUD_COUNT_reg_n_0_[5] }));
  FDRE #(
    .INIT(1'b0)) 
    \BAUD_COUNT_reg[9] 
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(BAUD_COUNT[9]),
        .Q(\BAUD_COUNT_reg_n_0_[9] ),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \DATA[7]_i_1 
       (.I0(STATE[1]),
        .I1(STATE[3]),
        .I2(IN1_ACK),
        .I3(IN1_STB),
        .I4(STATE[2]),
        .I5(STATE[0]),
        .O(\DATA[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \DATA_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\DATA[7]_i_1_n_0 ),
        .D(Q[0]),
        .Q(\DATA_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \DATA_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\DATA[7]_i_1_n_0 ),
        .D(Q[1]),
        .Q(p_6_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \DATA_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\DATA[7]_i_1_n_0 ),
        .D(Q[2]),
        .Q(p_5_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \DATA_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\DATA[7]_i_1_n_0 ),
        .D(Q[3]),
        .Q(p_4_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \DATA_reg[4] 
       (.C(ETH_CLK_OBUF),
        .CE(\DATA[7]_i_1_n_0 ),
        .D(Q[4]),
        .Q(p_3_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \DATA_reg[5] 
       (.C(ETH_CLK_OBUF),
        .CE(\DATA[7]_i_1_n_0 ),
        .D(Q[5]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \DATA_reg[6] 
       (.C(ETH_CLK_OBUF),
        .CE(\DATA[7]_i_1_n_0 ),
        .D(Q[6]),
        .Q(p_1_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \DATA_reg[7] 
       (.C(ETH_CLK_OBUF),
        .CE(\DATA[7]_i_1_n_0 ),
        .D(Q[7]),
        .Q(p_0_in),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h07)) 
    \FSM_sequential_STATE[0]_i_1 
       (.I0(STATE[2]),
        .I1(STATE[3]),
        .I2(STATE[0]),
        .O(\FSM_sequential_STATE[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h152A)) 
    \FSM_sequential_STATE[1]_i_1 
       (.I0(STATE[0]),
        .I1(STATE[2]),
        .I2(STATE[3]),
        .I3(STATE[1]),
        .O(\FSM_sequential_STATE[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0078)) 
    \FSM_sequential_STATE[2]_i_1 
       (.I0(STATE[1]),
        .I1(STATE[0]),
        .I2(STATE[2]),
        .I3(STATE[3]),
        .O(\FSM_sequential_STATE[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0F00FF010F00FE00)) 
    \FSM_sequential_STATE[3]_i_1 
       (.I0(STATE[0]),
        .I1(STATE[1]),
        .I2(STATE[2]),
        .I3(X16CLK_EN_reg_n_0),
        .I4(STATE[3]),
        .I5(S_IN1_ACK1),
        .O(\FSM_sequential_STATE[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0870)) 
    \FSM_sequential_STATE[3]_i_2 
       (.I0(STATE[1]),
        .I1(STATE[0]),
        .I2(STATE[3]),
        .I3(STATE[2]),
        .O(\FSM_sequential_STATE[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_sequential_STATE[3]_i_3 
       (.I0(IN1_ACK),
        .I1(IN1_STB),
        .O(S_IN1_ACK1));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_STATE_reg[0] 
       (.C(ETH_CLK_OBUF),
        .CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
        .D(\FSM_sequential_STATE[0]_i_1_n_0 ),
        .Q(STATE[0]),
        .R(INTERNAL_RST_reg));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_STATE_reg[1] 
       (.C(ETH_CLK_OBUF),
        .CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
        .D(\FSM_sequential_STATE[1]_i_1_n_0 ),
        .Q(STATE[1]),
        .R(INTERNAL_RST_reg));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_STATE_reg[2] 
       (.C(ETH_CLK_OBUF),
        .CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
        .D(\FSM_sequential_STATE[2]_i_1_n_0 ),
        .Q(STATE[2]),
        .R(INTERNAL_RST_reg));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_STATE_reg[3] 
       (.C(ETH_CLK_OBUF),
        .CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
        .D(\FSM_sequential_STATE[3]_i_2_n_0 ),
        .Q(STATE[3]),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFD00000003)) 
    S_IN1_ACK_i_1
       (.I0(IN1_STB),
        .I1(STATE[1]),
        .I2(STATE[3]),
        .I3(STATE[2]),
        .I4(STATE[0]),
        .I5(IN1_ACK),
        .O(S_IN1_ACK_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    S_IN1_ACK_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(S_IN1_ACK_i_1_n_0),
        .Q(IN1_ACK),
        .R(INTERNAL_RST_reg));
  LUT6 #(
    .INIT(64'hFFAAAABA00AAAA8A)) 
    TX_i_1
       (.I0(TX_reg_i_2_n_0),
        .I1(STATE[1]),
        .I2(STATE[0]),
        .I3(STATE[3]),
        .I4(STATE[2]),
        .I5(RS232_TX_OBUF),
        .O(TX_i_1_n_0));
  LUT6 #(
    .INIT(64'h0AC0FFFF0AC00000)) 
    TX_i_3
       (.I0(p_4_in),
        .I1(p_0_in),
        .I2(STATE[3]),
        .I3(STATE[2]),
        .I4(STATE[1]),
        .I5(TX_i_5_n_0),
        .O(TX_i_3_n_0));
  LUT6 #(
    .INIT(64'h0AFCFFFF0AFC0000)) 
    TX_i_4
       (.I0(p_3_in),
        .I1(\DATA_reg_n_0_[0] ),
        .I2(STATE[3]),
        .I3(STATE[2]),
        .I4(STATE[1]),
        .I5(TX_i_6_n_0),
        .O(TX_i_4_n_0));
  LUT4 #(
    .INIT(16'h0ACF)) 
    TX_i_5
       (.I0(p_6_in),
        .I1(p_2_in),
        .I2(STATE[3]),
        .I3(STATE[2]),
        .O(TX_i_5_n_0));
  LUT4 #(
    .INIT(16'h30BB)) 
    TX_i_6
       (.I0(p_5_in),
        .I1(STATE[2]),
        .I2(p_1_in),
        .I3(STATE[3]),
        .O(TX_i_6_n_0));
  FDSE #(
    .INIT(1'b1)) 
    TX_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(TX_i_1_n_0),
        .Q(RS232_TX_OBUF),
        .S(INTERNAL_RST_reg));
  MUXF7 TX_reg_i_2
       (.I0(TX_i_3_n_0),
        .I1(TX_i_4_n_0),
        .O(TX_reg_i_2_n_0),
        .S(STATE[0]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT2 #(
    .INIT(4'h1)) 
    X16CLK_EN_i_1__0
       (.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
        .I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
        .O(X16CLK_EN_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    X16CLK_EN_reg
       (.C(ETH_CLK_OBUF),
        .CE(1'b1),
        .D(X16CLK_EN_i_1__0_n_0),
        .Q(X16CLK_EN_reg_n_0),
        .R(INTERNAL_RST_reg));
endmodule

module user_design
   (IN1_STB,
    OUT1_ACK,
    output_rs232_out,
    INTERNAL_RST_reg,
    OUT1,
    IN1_ACK,
    ETH_CLK_OBUF,
    OUT1_STB);
  output IN1_STB;
  output OUT1_ACK;
  output [7:0]output_rs232_out;
  input INTERNAL_RST_reg;
  input [7:0]OUT1;
  input IN1_ACK;
  input ETH_CLK_OBUF;
  input OUT1_STB;

  wire ETH_CLK_OBUF;
  wire IN1_ACK;
  wire IN1_STB;
  wire INTERNAL_RST_reg;
  wire [7:0]OUT1;
  wire OUT1_ACK;
  wire OUT1_STB;
  wire [7:0]output_rs232_out;

  main_0 main_0_139931273178792
       (.ETH_CLK_OBUF(ETH_CLK_OBUF),
        .IN1_ACK(IN1_ACK),
        .IN1_STB(IN1_STB),
        .INTERNAL_RST_reg(INTERNAL_RST_reg),
        .OUT1(OUT1),
        .OUT1_ACK(OUT1_ACK),
        .OUT1_STB(OUT1_STB),
        .output_rs232_out(output_rs232_out));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
